IP 商城

Latest & Hot μIP :



商城 > IP 商城

    
PCI Express Gen4 PHY IP in TSMC 12nm FFC 参考报价 无资料 25 MHz 12 nm  
The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. 概述
PCI Express Gen4 PHY IP in 28nm HPC+ 参考报价 无资料 25 MHz 28 nm  
The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. 概述
DSP-BASED ETHERNET TRANSCEIVER in UMC 28nm HPC+ 参考报价 无资料 25 MHz 28 nm  
A 28nm DPS-based Gigabit Ethernet transceiver. Highly intergrated 1000BASE-T, 100BASE-TX, 100BASE-FX and 10BASE-Te. Fully compliant with 100BASE-FX IEEE 802.2u standard 概述
MIPI M-PHY Gear 4 IP in TSMC 12nm FFC 参考报价 无资料 11 GHz 12 nm  
MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. 概述
10/100/1000 Gigabit Ethernet Transceiver 参考报价 无资料 无资料 无资料  
The MIPG PHY is part of the A family of devices - which includes the MIPG PHY-031, MIPG PHY-033, and the MIPG PHY. It is A company’ 4th generation, single port 10/100/1000 Mbps Tri-speed Ethernet PHY. It supports RGMII interface to the MAC.™ The MIPG PHY provides a low power, low BOM (Bill of Materials) cost solution for comprehensive applications including consumer, enterprise, carrier and home networks such as PC, HDTV, Gaming machines, Blue-ray players, IPTV STB, Mdia Players, IP Cameras, NAS, Printers, Digital Photo Frames, MoCA/Homeplug (Powerline)/EoC/ adapters and Home Router & Gateways, etc. 概述
USB 3.0 PHY in 110nm 参考报价 1.000 M μm^2 25 Hz 110 nm  
    The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification.  This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The  IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. 概述
Rapid IO PHY in 65nm 参考报价 2.295 μm^2 25 Hz 65 nm  
    The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). 概述
USB2.0 UTMI Device PHY(non-oscillator) 100000 点 280.000 K μm^2 30.6 MHz 40 nm  
The USB PHY is an UTMI compatible USB2.0 device PHY IP which does not  require external oscillator reference. It is comprised of both USB1.1 and USB2.0  transceivers and it is also comprised of digital logic needed to convert USB serial  data to 8 or 16 bit parallel data. 概述
USB2.0 OTG PHY in 40 nm 80000 点 257.556 K μm^2 30.6 MHz 40 nm  
The IP is an UTMI+ Level 3 compatible USB2.0 OTG function  transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis  comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel  data for high speed and full speed. It is also support full speed and low speed  serial mode. 概述
微IP 价格 逻辑闸数 工作频率 工艺   评价