PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process
A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz.
This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process.
It can be integrated into a chip to generate an accurate clock.
PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process
A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz.
This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process.
It can be integrated into a chip to generate a high-speed clock.
The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz.
PLL 800M UMC 28 nm logic and Mixed-Mode HPC process
It is a 28-nm low-power spread spectrum clock generator that supports an operating frequency ranging from 400 MHz to 800 MHz and from 200 MHz to 400 MHz.
This SSCG is programmable to perform the frequency synthesis and spread-spectrum function for the Electro Magnetic Interference (EMI) reduction in various ASIC designs.
The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source. This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider. This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃.
The frequency synthesizer uses a single 1.25V power supply. Good noise immunity allows this IP to be integrated in a noisy SOC environment. The synthesizer operates at 1.5X WiFi 2.4GHz band for wireless application.