1. 概述:
This IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder.
The data interfaces in the JPEG Encoder IP Core (JPEGE) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects.
In order to let you assess the properties of the on-the-fly selectable quality setting, please use the slider below the image in order to see the final compressed image and compression ratio.
The JPEG Encoder IP Core has a real throughput of two compressed pixels every three clock cycles at any compression ratio for a chroma subsampling of 4:2:0. To calculate the throughput for your platform.
2. 售价:
参考报价
允许多个授权 : 否
3. 工作频率:
250 MHz
4. 逻辑闸数:
无资料
5. 工艺:
130 nm
6. 版本:
1.0