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  • 微IP名称: 8/12-bit JPEG decoder for ASIC and FPGA with scalable
  • 微IP编号: 386185029
  • 微IP种类: Digital μIP
  • 硬体描述语言: Verilog
  • 保固: 是
  • 仿真工具: Cadence NC-Verilog
  • 仿真工具版本:
  • 设计型式: RTL and Netlist
  • GDSII在晶圆厂合并: 否
  • 会员编号:6532486000200834
  • 卖家评价:
  • 参与评价总人数:有0人

1. 概述:

This JPEG decompression IP core supports the Baseline Sequential DCT and Extend- ed Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extreme- ly high pixel rates.

The JPEG-ST-V Decoder decompresses JPEG images and the video payload for Mo- tion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.

Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-MT-V Encoder Core. This Encoder-Decoder pair pro- vide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.

Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro- cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.

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