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  • 微IP名称: 3 mA Capless LDO in 40 nm (VLDS0003LNT040)
  • 微IP编号: 1031165646
  • 微IP种类: Analog μIP
  • 硬体描述语言: Verilog Behavioral Model
  • 保固: 否
  • 仿真工具: Cadence NC-Verilog
  • 仿真工具版本:
  • 设计型式: GDS & Schematic
  • GDSII在晶圆厂合并: 否
    贩售者资讯
  • 会员编号:2022490000500561
  • 卖家评价:
  • 参与评价总人数:有0人
 

1. 概述:

Power Quencher® Capless LDO (Silicon-proven 40 nm, 3 mA, excellent quiescent current for IoT)

This series of low-power, fully-integrated low dropout (LDO) voltage regulators achieves a low-noise output voltage without external components, thus saving package pins and valuable PC board space. These LDOs are silicon-proven in a 40 nm process and are a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications.


2. 售价:

参考报价

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3. 试用价:

参考报价


4. 工作频率:

无资料


5. 面积:

无资料


6. 工艺:

40 nm


7. 版本:

1.0