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  • 微IP名称: Digital Down Converter with configurable Decimation Filter
  • 微IP编号: 372396385
  • 微IP种类: Digital μIP
  • 硬体描述语言: Verilog
  • 保固: 是
  • 仿真工具: Cadence NC-Verilog
  • 仿真工具版本:
  • 设计型式: RTL
  • GDSII在晶圆厂合并: 否
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  • 会员编号:7730998000300188
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  • 参与评价总人数:有0人
 

1. 概述:

DDC is a complex-valued digital down-converter with a configurable number of decimation stages.  The design is ideal for high sample-rate applications and permits a digital input signal to be mixed-
down and re-sampled at a lower data rate.  The DDC is suitable for the down-conversion   of   any   digitally   modulated   signal   to   baseband   –   an essential step before digital processing.

The DDC features a high-precision 16-bit DDS oscillator for the digital mixing stage.   This oscillator is fully programmable and offers excellent phase and frequency resolution.  The digital mixing stage  is a complex multiplier that allows  the mixing of both real and imaginary (I/Q) inputs.  If only real inputs are required, then the imaginary input (q_in) should be tied low.

The output decimation stage features a configurable decimate-by-2N  poly-phase   filter   for   both   I   and   Q   channels.     Each   filter   stage   is   highly optimized to use only 12 multipliers while still achieving 80 dB of stop-band attenuation.

 

Application

  • Compatible with any digital modulation scheme - e.g. QPSK, BPSK, QAM, WiMAX, WCDMA, COFDM etc.
  • Conversion of IF signals to baseband frequencies for subsequent processing
  • Digital I/Q Demodulators

 

 


2. 售价:

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3. 工作频率:

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5. 工艺:

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6. 版本:

1.0