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| Clock divider by 3 | 100 点 | 52.000 Gates | 370 MHz | 130 nm |  |
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| There are 2 types of circuits in digital logic world. One is combinational, and the other is sequential. The difference between them is that the latter one has storage (memory) while the former one does not. Thus, in contrast to combinational circuits, whose output depends only on the current values of its inputs, the output of sequential circuits depends not only on the current values of its inputs but also on the past values of them. Based on the characteristic of sequential circuits, we can build counters. In addition, we can further build clock dividers with the counters we designed | 概述 | |||||
| Low power oscillator | 12000 点 | 100.100 μm^2 | 32 KHz | 40 nm | |
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| OSC32K is designed for 40nm advance process with 1.2v to 3.3v wide power(VDD) range. | 概述 | |||||
| 10-Bit 165 MSPS ADC in TSMC110nm | 参考报价 | 210.000 μm^2 | 165 MHz | 110 nm | |
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| MIC_ADC10 is compact and low power 10-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture and it is optimized for low power Figure 1. BLOCK DIAGRAM and small area. | 概述 | |||||
| PLL 800M UMC 28 nm logic and Mixed-Mode HPC process | 参考报价 | 230.000 μm^2 | 800 MHz | 28 nm | |
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| It is a 28-nm low-power spread spectrum clock generator that supports an operating frequency ranging from 400 MHz to 800 MHz and from 200 MHz to 400 MHz. This SSCG is programmable to perform the frequency synthesis and spread-spectrum function for the Electro Magnetic Interference (EMI) reduction in various ASIC designs. | 概述 | |||||
| PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process | 参考报价 | 230.000 μm^2 | 2 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate an accurate clock. | 概述 | |||||
| SPI slave in mode 2 | 1000 点 | 254.000 Gates | 192 MHz | 130 nm | |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | 概述 | |||||
| SPI slave in mode 3 | 1000 点 | 256.000 Gates | 285 MHz | 130 nm | |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it.The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions:The typical SPI bus architecture is designed as follows:When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line.With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | 概述 | |||||
| PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process | 参考报价 | 270.000 μm^2 | 1.6 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz. This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate a high-speed clock. The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz. | 概述 | |||||
| SPI slave in mode 0 | 1000 点 | 274.000 Gates | 243 MHz | 130 nm | |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | 概述 | |||||
| SPI slave in mode 1 | 1000 点 | 276.000 Gates | 285 MHz | 130 nm | |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | 概述 | |||||
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