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| USB 3.0 PHY in 110nm | 参考报价 | 1.000 M μm^2 | 25 Hz | 110 nm |  |
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| The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification. This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. | 概述 | |||||
| 14-Bit 3 MSPS ADC in GSMC110nm | 参考报价 | 322.000 K μm^2 | 3 MHz | 110 nm | |
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| MCR_GS110_ADC14 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. | 概述 | |||||
| 10-Bit 1MSPS Cyclic A/D Converter | 参考报价 | 300.500 K μm^2 | 10.12 Hz | 250 nm | |
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| This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range. The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz | 概述 | |||||
| 8-Bit 7 GSPS SAR ADC | 参考报价 | 300.000 K μm^2 | 7 GHz | 16 nm | |
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| This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area. APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition | 概述 | |||||
| USB2.0 UTMI Device PHY(non-oscillator) | 100000 点 | 280.000 K μm^2 | 30.6 MHz | 40 nm | |
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| The USB PHY is an UTMI compatible USB2.0 device PHY IP which does not require external oscillator reference. It is comprised of both USB1.1 and USB2.0 transceivers and it is also comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel data. | 概述 | |||||
| USB2.0 OTG PHY in 40 nm | 80000 点 | 257.556 K μm^2 | 30.6 MHz | 40 nm | |
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| The IP is an UTMI+ Level 3 compatible USB2.0 OTG function transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel data for high speed and full speed. It is also support full speed and low speed serial mode. | 概述 | |||||
| 12-Bit 320MSPS IQ DAC in IBM SOI 180nm | 参考报价 | 254.000 K μm^2 | 320 MHz | 180 nm | |
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| MIC_DAC12X2 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. | 概述 | |||||
| 12-Bit 320MPS IQ DAC in TSMC40LP | 70000 点 | 250.000 K μm^2 | 320 MHz | 180 nm | |
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| UIP_DAC12X2_320M_922687 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. This IQ DAC IP is optimized for low power and small area. At 320 MHz conversation rate, it only consumes 63mW and occupies silicon area of 0.25 mm2. APPLICATIONS WiFi / LTE / WiMax Wireless MIMO Digital Video Communication Transmit | 概述 | |||||
| 10-bit 165 MSPS ADC IP in 130 nm | 70000 点 | 210.000 K μm^2 | 165 MHz | 130 nm | |
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| UIP_ADC10_165M_166413 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_166413 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT | 概述 | |||||
| 10-bit 80 MSPS ADC IP in 130 nm | 60000 点 | 210.000 K μm^2 | 80 MHz | 130 nm | |
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| UIP_ADC10_80M_156287 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_80M_156287 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel | 概述 | |||||
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