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| IIR filter Second-Order | 参考报价 | 无资料 | 150 MHz | 无资料 |  |
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| This IP is a second order IIR filter sometimes referred to as a 'bi-quad'. Internally, it has a fully pipelined architecture permitting the highest possible sample rates for IIR filtering. Values are sampled on the rising clock-edge of clk when EN is high. The latency of the IIR filter between the first input sample and the first output sample is 7 clock cycles. Applicaion IIR filtering in higher sample-rate applications General purpose high-pass, band-pass and low-pass filters | 概述 | |||||
| High-speed FIR Filter with symmetry | 参考报价 | 无资料 | 500 MHz | 无资料 | |
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| This IP is an FIR filter IP Core with symmetrical coefficients and an even or odd number of filter taps. The architecture exploits the symmetry of the coefficients using half the number of multipliers compared to a normal FIR implementation. The result is a filter with a reduced area footprint while still maintaining the capacity for high sample rates. Application High-speed filter applications where resources are limited General purpose FIR filters with symmetrical coefficients | 概述 | |||||
| 2.4G PLL(UMC 28nm HPC) | 参考报价 | 24.000 K μm^2 | 2.4 GHz | 28 nm | |
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| Clock output 2.4GHz Input clock 10 ~ 50MHz Current consumption: < 4mA Supply: 1.8V / 0.9V UMC 28nm HPC | 概述 | |||||
| Binary FSK Demodulator | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| This IP is a precision Binary-FSK Demodulator IP Core based on a non-coherent receiver design. The demodulator is fully programmable, allowing for a varied range of symbol rates and mark/space tone frequencies. Input data samples may be either complex or real for support of either passband or baseband signals. The module allows easy connectivity to an external ADC with up to 16-bit signed input samples. Applications: Short range telemetry Software radio | 概述 | |||||
| 影音开发平台 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| Single Chip Solution 32-bit RISC MCU SPI/UART/I2C/GPIO Video Process Engine Video DAC/Audio DAC USB 2.0 Video Scaler DDR4 Easy Integrated Customer’s Logic Application DVR and POS DVR ATM machine surveillance Home stay monitoring Multiple channel IP camera | 概述 | |||||
| H.264 Encoder IP Core | 参考报价 | 无资料 | 150 MHz | 无资料 | |
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| This H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. The IP offers two encoder variants to meet the different targets of features. The IP include 2 mode. H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes) The IP core is smaller but yields less compression. It does not require external memory. H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile: The IP core is larger but offers a significantly better compression. Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle. The data interfaces in the H.264 Encoder IP Core use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. | 概述 | |||||
| JPEG Encoder | 参考报价 | 无资料 | 250 MHz | 130 nm | |
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| This IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder. The data interfaces in the JPEG Encoder IP Core (JPEGE) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. In order to let you assess the properties of the on-the-fly selectable quality setting, please use the slider below the image in order to see the final compressed image and compression ratio. The JPEG Encoder IP Core has a real throughput of two compressed pixels every three clock cycles at any compression ratio for a chroma subsampling of 4:2:0. To calculate the throughput for your platform. | 概述 | |||||
| JPEG Decoder | 参考报价 | 无资料 | 250 MHz | 130 nm | |
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| This JPEG Decoder IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Decompressor / Decoder. When decoding JPEG images, pixel throughput can not be fixed for compressed JPEGs of arbitrary quality, as it depends on the compression ratio (bits needed to encode one pixel). To circumvent this limitation JPEG Decoder IP features a dual pixel component pipeline, allowing for greater decoding speeds. | 概述 | |||||
| 10/100/1000 Ethernet Media Access Controller | 参考报价 | 无资料 | 125 MHz | 130 nm | |
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| The MAC-1G/MAC is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by the IEEE 802.3 standard for media access control over the 10Mbps, 100Mbps and 1Gbps Ethernet. Communication with an external host is implemented via a set of Control and Status Registers and the DMA controller for external shared RAM memory. For data transfers the MAC-1G/MAC operates as a DMA master. It automatically fetches from transmit data buffers and stores receive data buffers into external RAM with minimum CPU intervention. The linked list management enables the use of various memory allocation schemes. There is an interface for external dual port RAMs serving as configurable FIFO memories and there are separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC-1G/MAC from an external host and provides resolution in case of latency of an external bus. Application Network Interface Cards (NICs) Routers, switching hubs | 概述 | |||||
| Oscillator - RC22MHz | 参考报价 | 无资料 | 22 MHz | 180 nm | |
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| The RC_OSC22M is a low power consumption internal Resistor/Capacitor oscillator with trimming operating frequency. This OSC needs input Bandgap reference voltage to maintain stable operating frequency and decrease power supply effects. The RC-oscillator cell is useful for applications that require an oscillator that utilizes non-external components and has a relaxed frequency tolerance. An enable / disable mode is provided to disable the oscillator. When the oscillator is in the disable mode, the output (CLK22M) goes to a logic level low. It is processed using SMIC’s 0.35μm logic process with an operating supply voltage range of 2.0V ~ 5.5V and a junction temperature range of -40˚ ~ 125˚C. | 概述 | |||||
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