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| Chroma Resampler | 参考报价 | 无资料 | 400 MHz | 无资料 |  |
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| The IP Core is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colour space. In total, the IP Core package contains two distinct modules – one module that converts from 4:4:4 to 4:2:2 and the other that performs the reciprocal operation from 4:2:2 to 4:4:4. Pixels flow into the design in accordance with the valid ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when PIX_VALID and PIX_READY are both high. At the output interface, pixels and syncs are sampled on a the rising edge of clk when POUT_VALID and POUT_READY are high. The input and output sync signals are coincident with the first pixel of a frame and the first pixel of a line. These are useful to identify the video frame and line boundaries. Application Digital video and image processing Interfacing between different video processing and video transceiver ICs that use different colour formats | 概述 | |||||
| 4K/8k capable JPEG Encoder with scalable | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This JPEG compression IP core supports the Baseline Sequential DCT and the Ex- tended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less pow- er than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-MT-V Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame vid- eo. Once programmed, the easy-to-use encoder requires no assistance from a host pro- cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed da- ta, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Stream- ing interface. | 概述 | |||||
| 8/12-bit JPEG decoder for ASIC and FPGA with scalable | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This JPEG decompression IP core supports the Baseline Sequential DCT and Extend- ed Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extreme- ly high pixel rates. The JPEG-ST-V Decoder decompresses JPEG images and the video payload for Mo- tion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-MT-V Encoder Core. This Encoder-Decoder pair pro- vide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro- cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. | 概述 | |||||
| 10/100/1000 Gigabit Ethernet Transceiver | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| The MIPG PHY is part of the A family of devices - which includes the MIPG PHY-031, MIPG PHY-033, and the MIPG PHY. It is A company’ 4th generation, single port 10/100/1000 Mbps Tri-speed Ethernet PHY. It supports RGMII interface to the MAC.™ The MIPG PHY provides a low power, low BOM (Bill of Materials) cost solution for comprehensive applications including consumer, enterprise, carrier and home networks such as PC, HDTV, Gaming machines, Blue-ray players, IPTV STB, Mdia Players, IP Cameras, NAS, Printers, Digital Photo Frames, MoCA/Homeplug (Powerline)/EoC/ adapters and Home Router & Gateways, etc. | 概述 | |||||
| High Stable Timers IP | 参考报价 | 无资料 | 0.8 MHz | 无资料 | |
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| Timers are used for scheduling the different activities within the system. Timers generates interrupt in system and Operating system(OS) Schedules different Timers and maps them to different Interrupt Service Routine (ISR) to start on different interrupts. It can happen before starting a activity or application, OS configures a timers and give control to application to operate. On Interrupt trigger a interrupt, ISR kicks in and passes control back to OS. A Miss Function on this block can make system to mis-behave a lot. These section explains issues with normal timers and benefits of this high stable timers over conventional timers. -The Problem with Current Technology Timers carry large counters, Registers, clocks pre-scalers and synchronizations and all these are built by Simple Components which do not have any stability. If the SOC is exposed to different hazards like radiations, sparks or other events. These logics can be corrupted within counters and registers carrying configuration. This may result in corruption in stored configurations or counters or data or control passing by and can make interrupts to be generated fast or slower rate or even stopped. If system gets faster interrupt, then expected will make control to passed back to Operating system(OS) from the application or much before the application actually able to complete the task. This make system to not able to perform the required task. if interrupts generation is slowed down, will keep the OS waiting much longer to get control and application work is finished long back. This can make system to slow down or Hang. -The Solution High Stable Timers from GreenIPCore can sustain across all system un-stability and misbehavior problems. This Timers is strengthening system against any kind of dirty Electromagnetic noise and capable of protecting the System operation without disruption. The Timers is constructed with high stable components. The High Stable Timers shown above will not fail due to any hazardous event. | 概述 | |||||
| High Speed CAN Transceiver | 参考报价 | 无资料 | 1 MHz | 无资料 | |
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| The MX102 is the interface between the Controller Area Network (CAN) protocol controller and the physical bus. It is primarily intended for high speed applications, up to 1 Mbps, in passenger cars. The device provides differential transmit capability to the bus and differential receive capability to the CAN controller. The MX102 also features a very low current standby mode with remote wake up capability via the bus. | 概述 | |||||
| BOSCH CAN 2.0A/B AND CAN FD 1.0 CONTROLLER | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| The CAN controller is an I2C/APB compliant controller to act as a transmitter or receiver in the CAN bus. | 概述 | |||||
| CAN 2.0 & CAN FD Bus Controller Core | 参考报价 | 12.000 K Gates | 无资料 | 无资料 | |
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| The CAN protocol uses a multi-master bus configuration for the transfer of frames be- tween nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between vari- ous components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames. The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It imple- ments a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application | 概述 | |||||
| Octal SPI Master/Slave Controller | 参考报价 | 4.641 K Gates | 500 MHz | 无资料 | |
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| Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the most significant bit position in a frame, serial clock phase and polarity are all software- programmable. In master mode the core can control up to 32 slaves. A software controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose | 概述 | |||||
| USB 2.0 ON-THE-GO CONTROLLER | 参考报价 | 75.000 K Gates | 200 MHz | 无资料 | |
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| This is a universal serial bus (USB) 2.0 On-The-Go (OTG) Controller, which can play dual-role, as a host or a device controller. When it acts as a host, it contains a USB host controller to support all speed transactions. | 概述 | |||||
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