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10-Bit 1MSPS Cyclic A/D Converter 参考报价 300.500 K μm^2 10.12 Hz 250 nm  
  This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range. The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz 概述
Configurable Reed Solomon Encoder 30000 点 2.500 K Gates 250 MHz 180 nm  
Our IP core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It  also  supports  varying  on  the  fly   shortened  codes.  Therefore  any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst  decoding.  The  implementation  is  very  low  latency,  high  speed with a simple interface for easy integration in SoC applications. 概述
AES Codec with 8-bit datapath 20000 点 1.300 K Gates 515 MHz 180 nm  
The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed to require minimum logic resources rendering it an ideal solution for low power applications. This has been achieved by using an 8-bit data path size which means that 16 clock cycles are required to load/unload the 128-bit plaintext/ciphertext block. The encryptor receives the 128-bit plaintext block in 8-bit input symbols and generates the corresponding 128-bit ciphertext block in 8-bit output symbols using a supplied 128, 192, or 256-bit AES key. The pre-computed key values are read from an internal round key RAM. A key expander module is provided as an optional module to allow automatic generation and loading of the round key RAM. The decryptor implements the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications.  概述
AES Codec with 128-bit datapath 20000 点 22.000 K Gates 260 MHz 180 nm  
The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of  data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed for high throughput applications with optimal logic resources utilization. The encryptor core accepts a 128-bit plaintext input word, and generates a corresponding 128-bit ciphertext output word using a supplied 128, 192, or 256-bit AES key. The decryptor core provides the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The hardware roundkey expansion logic has been designed as a discrete building block. This allows either to build a complete stand-alone AES solution, or to save logic resources by leaving the key generation process to the user. Alternatively, the roundkey expansion logic can be shared between multiple encryption/decryption cores for optimal silicon area resources utilization. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications.  概述
12-Bit 320MPS IQ DAC in TSMC40LP 70000 点 250.000 K μm^2 320 MHz 180 nm  
UIP_DAC12X2_320M_922687  is  compact  and low  power  12-bit  digital-to-analog  converter silicon  IP  in  IBM  180nm  SOI  process.  It features two channel current steering DAC.  This  IQ  DAC  IP  is  optimized  for  low  power and  small  area.  At  320  MHz  conversation rate,  it  only  consumes  63mW  and  occupies silicon area of 0.25 mm2.   APPLICATIONS​ WiFi / LTE / WiMax​ Wireless MIMO Digital Video Communication Transmit   概述
12-Bit 800KSPS Low Power SAR-ADC 参考报价 无资料 25 MHz 180 nm  
The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC   and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. 概述
32 bits RISC Microcontroller 参考报价 33.000 K Gates 100 MHz 180 nm  
The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces. Applications Wearables IoT Motor Control Appliances Connectivity Smart home/building/enterprice/planet 概述
Oscillator - RC22MHz 参考报价 无资料 22 MHz 180 nm  
The RC_OSC22M is a low power consumption internal Resistor/Capacitor oscillator with trimming operating frequency.  This OSC needs input Bandgap reference voltage to maintain stable operating frequency and decrease power supply effects.  The RC-oscillator cell is useful for applications that require an oscillator that utilizes non-external components and has a relaxed frequency tolerance.  An enable / disable mode is provided to disable the oscillator.  When the oscillator is in the disable mode, the output (CLK22M) goes to a logic level low.  It is processed using SMIC’s 0.35μm logic process with an operating supply voltage range of 2.0V ~ 5.5V and a junction temperature range of -40˚ ~ 125˚C. 概述
12-Bit 50 MSPS ADC in IBM 180 SOI 参考报价 280.000 μm^2 50 MHz 180 nm  
MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area. 概述
300 mA Capless LDO in 180 nm (VLDS0300RNM180) 参考报价 无资料 无资料 180 nm  
Noise Quencher® Capless LDO (Silicon-proven 180 nm, 300 mA, excellent supply noise rejection and fast settling) Noise Quencher® LDOs: This series of low-power, fully-integrated low dropout (LDO) voltage regulators uses our patented Noise Quencher® Technology to provide best-in-class dynamic performance and noise rejection. The IP cores are unconditionally stable across a wide range of load currents and load capacitances and also do not require external components, thus saving package pins and valuable PC board space. These LDOs are optimized for stand-alone power management integrated circuit (PMIC) ASSPs and other analog and digital applications. 概述
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