1. 概述：

Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the
most significant bit position in a frame, serial clock phase and polarity are all software- programmable. In master mode the core can control up to 32 slaves. A software controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose

 

2. 售价：

参考报价

允许多个授权 : 否

3. 工作频率：

500 MHz

4. 逻辑闸数：

4.641 K Gates

5. 工艺：

无资料

6. 版本：

1