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PCI Express Gen4 PHY IP in TSMC 12nm FFC 参考报价 无资料 25 MHz 12 nm  
The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. 概述
PCI Express Gen4 PHY IP in 28nm HPC+ 参考报价 无资料 25 MHz 28 nm  
The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. 概述
DSP-BASED ETHERNET TRANSCEIVER in UMC 28nm HPC+ 参考报价 无资料 25 MHz 28 nm  
A 28nm DPS-based Gigabit Ethernet transceiver. Highly intergrated 1000BASE-T, 100BASE-TX, 100BASE-FX and 10BASE-Te. Fully compliant with 100BASE-FX IEEE 802.2u standard 概述
10-Bit 165 MSPS ADC in TSMC110nm 参考报价 210.000 μm^2 165 MHz 110 nm  
MIC_ADC10 is compact and low power 10-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture and it is optimized for low power Figure 1. BLOCK DIAGRAM and small area. 概述
Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm 参考报价 330.000 μm^2 330 MHz 90 nm  
is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. 概述
MIPI M-PHY Gear 4 IP in TSMC 12nm FFC 参考报价 无资料 11 GHz 12 nm  
MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. 概述
12-Bit 320MSPS IQ DAC in IBM SOI 180nm 参考报价 254.000 K μm^2 320 MHz 180 nm  
MIC_DAC12X2 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. 概述
14-Bit 1MSPS DAC in GSMC110nm 参考报价 75.000 K μm^2 1 MHz 110 nm  
MIC_DAC14 is compact and low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from 1.7V to 5.6V. Its single-end output ranges from 0.1 to 0.9 of supply voltage. 概述
300 mA Capless LDO in 180 nm (VLDS0300RNM180) 参考报价 无资料 无资料 180 nm  
Noise Quencher® Capless LDO (Silicon-proven 180 nm, 300 mA, excellent supply noise rejection and fast settling) Noise Quencher® LDOs: This series of low-power, fully-integrated low dropout (LDO) voltage regulators uses our patented Noise Quencher® Technology to provide best-in-class dynamic performance and noise rejection. The IP cores are unconditionally stable across a wide range of load currents and load capacitances and also do not require external components, thus saving package pins and valuable PC board space. These LDOs are optimized for stand-alone power management integrated circuit (PMIC) ASSPs and other analog and digital applications. 概述
14-Bit 3 MSPS ADC in GSMC110nm 参考报价 322.000 K μm^2 3 MHz 110 nm  
MCR_GS110_ADC14 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. 概述
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