It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz.
允许多个授权 : 否
92.4 K μm^2