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  • 微IP名称: PLL 3000M UMC 28 nm logic and Mixed-Mode HPC process
  • 微IP编号: 1947570486
  • 微IP种类: Analog μIP
  • 硬体描述语言: Verilog Behavioral Model
  • 保固: 是
  • 仿真工具: Cadence NC-Verilog
  • 仿真工具版本:
  • 设计型式: LEF
  • GDSII在晶圆厂合并: 是
  • 会员编号:2804246000800625
  • 卖家评价:
  • 参与评价总人数:有0人

1. 概述:

It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz.

2. 售价:


允许多个授权 :

3. 试用价:


4. 工作频率:

27 MHz

5. 面积:

92.4 K μm^2

6. 工艺:

28 nm

7. 版本: