Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm |
参考报价 |
330.000 μm^2 |
330 MHz |
90 nm |
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is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format.
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概述 |
12-Bit 320MSPS IQ DAC in IBM SOI 180nm |
参考报价 |
254.000 K μm^2 |
320 MHz |
180 nm |
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MIC_DAC12X2 is compact and low power 12-bit digital-to-analog converter
silicon IP in IBM 180nm SOI process. It features two channel current steering DAC.
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概述 |
14-Bit 1MSPS DAC in GSMC110nm |
参考报价 |
75.000 K μm^2 |
1 MHz |
110 nm |
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MIC_DAC14 is compact and low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from 1.7V to 5.6V. Its single-end output ranges from 0.1 to 0.9 of supply voltage.
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概述 |
12-Bit 320MPS IQ DAC in TSMC40LP |
70000 点 |
250.000 K μm^2 |
320 MHz |
180 nm |
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UIP_DAC12X2_320M_922687 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC.
This IQ DAC IP is optimized for low power and small area. At 320 MHz conversation rate, it only consumes 63mW and occupies silicon area of 0.25 mm2.
APPLICATIONS
WiFi / LTE / WiMax
Wireless MIMO
Digital Video
Communication Transmit
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概述 |
14 Bit Rail to Rail DAC |
60000 点 |
75.000 K μm^2 |
1 MHz |
110 nm |
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UIP_DAC14_1M_392231 is compact and low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from 1.7V to 5.6V. Its single-end output ranges from 0.1 to 0.9 of supply voltage.
This DAC IP is self-biased and optimized for low power and small area. At 1 MHz conversation rate, it only consumes 680uA to drive 15K/50pF loading and occupies silicon area of 0.075 mm2.
APPLICATIONS
General purpose digital to analog converter
Battery monitory system
Housekeeping
Auxiliary functionality
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概述 |
10-bit 300 MSPS Video DAC IP in 90 nm |
60000 点 |
76.000 K μm^2 |
300 MHz |
90 nm |
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The UIP_DAC10-300M_205370 is a 10-bit DAC designed in low power TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2V, in unsigned format.
A 3.3V supply is used for the analog portion of the IP. This high performance DAC is designed for CVBS standard or RGB Video signal bandwidth. The IP consumes only 41 mA at 300 MSPS operation and utilizes a silicon area of only 0.076 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems.
The DAC output current is 6-bit programmable. The IP architecture is robust and can be ported to other 90 nm processes.
APPLICATIONS
Composite Video (CVBS)
HDTV
RGB Video
DAC Output Model
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概述 |