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  • 微IP名称: PCI Express Gen4 PHY IP in 28nm HPC+
  • 微IP编号: 920339388
  • 微IP种类: Analog μIP
  • 硬体描述语言: Verilog Behavioral Model
  • 保固: 是
  • 仿真工具: Cadence NC-Verilog
  • 仿真工具版本:
  • 设计型式: GDS & Schematic
  • GDSII在晶圆厂合并: 是
    贩售者资讯
  • 会员编号:2804246000800625
  • 卖家评价:
  • 参与评价总人数:有0人
 

1. 概述:

The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.


2. 售价:

参考报价

允许多个授权 :


3. 试用价:

参考报价


4. 工作频率:

25 MHz


5. 面积:

无资料


6. 工艺:

28 nm


7. 版本:

1.0