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The TDM-Rx-Pro is part of proven audio interface cores featuring a configurable multi-channel audio 参考报价 无资料 192 KHz 65 nm  
The TDM-Rx-Pro  is part of proven audio interface cores featuring a configurable multi-channel audio interface designed to input serial (TDM) digital audio streams from various manufacturers. The TDM-Rx-Pro front-end also supports the well known stereo formats: Philips I2S, Left-Justified or Right-Justified. The TDM-Rx-Pro backend is supplied with a choice of AMBA®, CoreConnect™ or a flexible parallel interface. 概述
ASRC-Lite : 16-bit -90dB THD+N Multi-Channel Audio Sample 参考报价 无资料 192 KHz 45 nm  
  The ASRC-lite  is part of multi-channel asynchronous Audio Sample Rate Converter (ASRC). This core can be used to interface digital audio equipments operating at different sample rates. It has been designed for systems that require a low-cost solution, maintaining low harmonic distortion and noise, and a high tolerance and rejection of input jitter. The ASRC-lite can perform common sample rate conversions with less than -90 dB of Total Harmonic Distortion plus Noise (THD+N) and has a Dynamic range of 92 dB, supporting input data of 16-bit resolution. The ASRC series are implemented to support several key industry interfaces: TDM parallel, TDM serial, Parallel, I2S, SPDIF-AES3. We offers a broad range of asynchronous sample rate converters targeted for variety of audio applications   Application : Set-top boxes, professional and hi-fi audio Home Theater Systems Automotive Audio Systems Digital Audio Effects Processors Digital Audio Broadcast Equipment 概述
ASRC-Pro : 24-bit -130dB THD+N Multi-Channel Audio Sample Rate Converter 参考报价 无资料 8.192 MHz 45 nm  
  The ASRC-pro is part of multi-channel Asynchronous Audio Sample Rate Converters (ASRC). This core can be used to interface digital audio equipments operating at different sample rates. It has been designed for systems requiring very high quality in terms of low harmonic distortion and noise, tolerance and rejection of input jitter. The ASRC-pro can perform common sample rate conversions with less than -130 dB of Total Harmonic Distortion plus Noise (THD+N) and has a Dynamic range of 131 dB, supporting input data processing of up to 24-bit resolution. The ASRC series are implemented to support several key industry interfaces: TDM parallel, TDM serial, Parallel, I2S, SPDIF-AES3. We offers a broad range of asynchronous sample rate converters targeted for variety of audio applications. Application: Set-top boxes, professional and hi-fi audio Home Theater Systems Automotive Audio Systems Digital Audio Effects Processors Digital Audio Broadcast Equipment 概述
High Speed CAN Transceiver 参考报价 无资料 1 MHz 无资料  
The MX102 is the interface between the Controller Area Network (CAN) protocol controller and the physical bus. It is primarily intended for high speed applications, up to 1 Mbps, in passenger cars. The device provides differential transmit capability to the bus and differential receive capability to the CAN controller. The MX102 also features a very low current standby mode with remote wake up capability via the bus. 概述
High Stable Timers IP 参考报价 无资料 0.8 MHz 无资料  
Timers are used for scheduling the different activities within the system. Timers generates interrupt in system and Operating system(OS) Schedules different Timers and maps them to different Interrupt Service Routine (ISR) to start on different interrupts. It can happen before starting a activity or application, OS configures a timers and give control to application to operate. On Interrupt trigger a interrupt, ISR kicks in and passes control back to OS. A Miss Function on this block can make system to mis-behave a lot. These section explains issues with normal timers and benefits of this high stable timers over conventional timers. -The Problem with Current Technology  Timers carry large counters, Registers, clocks pre-scalers and synchronizations and all these are built by Simple Components which do not have any stability.  If the SOC is exposed to different hazards like radiations, sparks or other events. These logics can be corrupted within counters and registers carrying configuration. This may result in corruption in stored configurations or counters or data or control passing by and can make interrupts to be generated fast or slower rate or even stopped. If system gets faster interrupt, then expected will make control to passed back to Operating system(OS) from the application or much before the application actually able to complete the task. This make system to not able to perform the required task. if interrupts generation is slowed down, will keep the OS waiting much longer to get control and application work is finished long back. This can make system to slow down or Hang. -The Solution High Stable Timers from GreenIPCore can sustain across all system un-stability and misbehavior problems. This Timers is strengthening system against any kind of dirty Electromagnetic noise and capable of protecting the System operation without disruption. The Timers is constructed with high stable components. The High Stable Timers shown above will not fail due to any hazardous event. 概述
8/12-bit JPEG decoder for ASIC and FPGA with scalable 参考报价 无资料 无资料 无资料  
This JPEG decompression IP core supports the Baseline Sequential DCT and Extend- ed Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extreme- ly high pixel rates. The JPEG-ST-V Decoder decompresses JPEG images and the video payload for Mo- tion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-MT-V Encoder Core. This Encoder-Decoder pair pro- vide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro- cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. 概述
4K/8k capable JPEG Encoder with scalable 参考报价 无资料 无资料 无资料  
This JPEG compression IP core supports the Baseline Sequential DCT and the Ex- tended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less pow- er than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-MT-V Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame vid- eo. Once programmed, the easy-to-use encoder requires no assistance from a host pro- cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed da- ta, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Stream- ing interface. 概述
Real-Time-Clock 参考报价 无资料 32 KHz 130 nm  
The RTC is a TSMC 0.13μm Real-Time-Clock cell that provides multiple clocks.   This RTC provides an operating voltage range of 2.7V ~ 3.3V, and an operating junction temperature range of -40˚ ~ 125℃. 概述
Chroma Resampler 参考报价 无资料 400 MHz 无资料  
The IP Core is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colour space. In total, the IP Core package contains two distinct modules – one module that converts from 4:4:4 to 4:2:2 and the other that performs the reciprocal operation from 4:2:2 to 4:4:4. Pixels flow into the design in accordance with the valid ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when PIX_VALID and PIX_READY are both high. At the output interface, pixels and syncs are sampled on a the rising edge of clk when POUT_VALID and POUT_READY  are high. The input and output sync signals are coincident with the first pixel of a frame and the first pixel of a line.  These are useful to identify the video frame and line boundaries.  Application Digital video and image processing Interfacing between different video processing and video transceiver ICs that use different colour formats 概述
Multi-format Video Deinterlacer 参考报价 无资料 200 MHz 无资料  
The IP Core is a high quality 24-bit RGB video deinterlacer capable of generating progressive output video at up to 4096x4096 pixels in resolution. The design is fully customizable, supporting any desired interlaced video format. The deinterlacer allows for three possible filter algorithms - either BOB, ELA  or  LCI. All three methods are 'intra-field' methods that perform spatial filtering within the same field.  For this reason, the output video is not subject to combing or tearing which is characteristic of a traditional 'weave' approach. Each algorithm has it relative merits in terms of image quality and hardware complexity. In particular, the enhanced LCI algorithm provides excellent all-round performance with reduced image softening and crisp clean edges.    Application Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips High-quality video de-interlacing without the overhead of a frame buffer Digital TV set-top boxes and home media solutions 概述
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