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| Color-space Converter | 参考报价 | 无资料 | 400 MHz | 无资料 |  |
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| This IP is a fully pipelined color-space converter that converts pixels between the RGB and YCbCr color spaces. In total, the IP Core package contains two distinct modules – one module that converts from 24-bit RGB to 30-bit 4:4:4 YCbCr and the other that performs the reciprocal operation from 4:4:4 YCbCr to RGB. Application Digital video and image processing | 概述 | |||||
| ITU-R BT.656 video decoder | 参考报价 | 无资料 | 300 Hz | 无资料 | |
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| DEC_BT656 is a digital video decoder with integrated colour-space converter. It's function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent processing. Pixels are extracted from the BT.656 input stream and converted to RGB888 format. Application BT.656 input video capture and processing PAL & NTSC SDTV interlaced format conversion | 概述 | |||||
| ITU-R BT.656 video encoder | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| ITU-R_BT is a digital video encoder with integrated colour-space converter. The encoder accepts 24-bit RGB pixels from sequential odd and even fields. These pixels are then mapped to the YCbCr colour-space and formatted correctly into a BT output stream. The output of the encoder generates an industry standard ITU-R BT.656 format video stream together with a video_val signal that is asserted with the first valid byte of the output stream. Applications BT.656 output video generation PAL & NTSC SDTV video format conversion | 概述 | |||||
| Video Frame Buffer | 参考报价 | 无资料 | 300 MHz | 无资料 | |
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| VID_FB is a high-speed multi-format video frame buffer that asynchronously samples an input video stream and buffers it in an external memory. Output pixels are read out of the buffer and synchronised to the system clock domain. The VID_FB will automatically adapt to different input and output frame rates. If the input frame rate is too high, then the VID_FB will cleanly drop or 'skip' an input frame. Likewise, if the output frame rate is higher than the input frame rate, then frames will be repeated 3 . The result is a system that seamlessly adapts to the different frame rates at the input and output of the VID_FB. Applications Buffering video frames in external memory Real-time digital video applications Genlocking of multiple video sources | 概述 | |||||
| 金融资讯安全开发平 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This Platform can decrease timing for develop. Single Chip Solution 32-bit RISC MCU SPI/UART/I2C/GPIO Crypto Engine PCIE Gen2/Gen3 USB 2.0 Flash Controller DDR4 Easy Integrated Customer’s Logic Applications Security Network Financial Information Security | 概述 | |||||
| 进阶物联网开发平台 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This Platform can decrease timing for develop. Single Chip Solution Integrated Gyroscope Sensor Integrated Acceleration Sensor Integrated Communication 32-bit RISC MCU ADC SPI/UART/I2C/GPIO Crypto Engine Easy Integrated Customer’s Logic Applications Security Systems Home and Building Automation IoT | 概述 | |||||
| 入门物联网开发平台 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This Platform can decrease timing for develop. Single Chip Solution Integrated Gyroscope Sensor Integrated Acceleration Sensor 32-bit RISC CPU ADC Wi-Fi/Bluetooth SPI/UART/I2C/GPIO Easy Integrated Customer’s Logic Applications Home and Building Automation Smart Energy Internet of Things | 概述 | |||||
| 车用电子开发平台 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| Single Chip Solution Integrated Pressure Sensor Integrated Acceleration Sensor Integrated Temperature Sensor 32-bit RISC CPU PWM RF Transmitter (300-450 Mhz) LF Receiver Easy Integrated Customer’s Logic Application Tire Pressure Monitoring System Automotive electronics | 概述 | |||||
| 8-bit / 16-bit Flash memory controller | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components . Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices. Applications Any application where non-volatile storage is required Offline storage of parameters and data via your Chip | 概述 | |||||
| DDR4 SDRAM Controller Core | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| Double Data Rate 4 (DDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time. The core supports all new DDR4 features, including: 3DS device configurations, write CRC, data bus inversion (DBI), fine granu-larity refresh, additive latency, per-DRAM addressability, and temperature controlled refresh. | 概述 | |||||
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