1. 概述：

A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz.

This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process.

It can be integrated into a chip to generate an accurate clock. 

2. 售价：

参考报价

允许多个授权 : 否

3. 试用价：

参考报价

4. 工作频率：

2 GHz

5. 面积：

230 μm^2

6. 工艺：

28 nm

7. 版本：

1