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  • 微IP名称: PLL 1300M UMC 28 nm logic and Mixed-Mode HPC process
  • 微IP编号: 417050153
  • 微IP种类: Analog μIP
  • 硬体描述语言: Verilog Behavioral Model
  • 保固: 是
  • 仿真工具: Cadence NC-Verilog
  • 仿真工具版本:
  • 设计型式: LEF
  • GDSII在晶圆厂合并: 是
  • 会员编号:2804246000800625
  • 卖家评价:
  • 参与评价总人数:有0人

1. 概述:

It is used to generate a stable, high-speed clock from an external slower clock signal. It integrates one Voltage-Controlled Oscillator (VCO), one Phase-Frequency Detector (PFD), one Low-Pass Filter (LPF), one 8-bit programmable divider, and other associated support circuitries. This PLL supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. This IP uses the input operating frequency of PFD ranging from 6 MHz to 25 MHz and generates the output frequency ranging from 25 MHz to 1300 MHz. 
The jitter performance of a PLL is highly dependent on the floor plan of ASIC. Because PLL is a sensitive cell when integrated into an ASIC design, the best way to maximize its capacity is to keep PLL away from the noisy blocks in the core region, such as the memory block and the high-driving logic circuit, and the I/O region, such as the high-driving I/O. This PLL must be placed around the I/O area. Providing sufficient space between this PLL and the noisy blocks is a simple and effective approach to reduce the coupled substrate noise.


2. 售价:


允许多个授权 :

3. 试用价:


4. 工作频率:

50 MHz

5. 面积:

109.85 K μm^2

6. 工艺:

28 nm

7. 版本: