1. 概述：

A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz.
This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process.
It can be integrated into a chip to generate a high-speed clock.
The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz.

2. 售价：

参考报价

允许多个授权 : 否

3. 试用价：

参考报价

4. 工作频率：

1.6 GHz

5. 面积：

270 μm^2

6. 工艺：

28 nm

7. 版本：

1