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  • 微IP名称: Clock divider by 3
  • 微IP编号: 271798
  • 微IP种类: Digital μIP
  • 硬体描述语言: Verilog
  • 保固: 是
  • 仿真工具: Cadence NC-Verilog
  • 仿真工具版本:
  • 设计型式: Netlist
  • GDSII在晶圆厂合并: 否
    贩售者资讯
  • 会员编号:7520023000300058
  • 卖家评价:
  • 参与评价总人数:有0人
 

1. 概述:

There are 2 types of circuits in digital logic world. One is combinational, and the other is sequential. The difference between them is that the latter one has storage (memory) while the former one does not. Thus, in contrast to combinational circuits, whose output depends only on the current values of its inputs, the output of sequential circuits depends not only on the current values of its inputs but also on the past values of them. Based on the characteristic of sequential circuits, we can build counters. In addition, we can further build clock dividers with the counters we designed


2. 售价:

100 点

允许多个授权 :

   - 2 ~ 5 个授权的折扣数:5 %
   - 6 ~ 10 个授权的折扣数:10 %
   - 大于 10 个授权的折扣数:15 %


3. 工作频率:

370 MHz


4. 逻辑闸数:

52 Gates


5. 工艺:

130 nm


6. 版本:

1.0