1. 概述：

The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source.  This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider.   This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃. 

2. 售价：

参考报价

允许多个授权 : 是

   - 2 ~ 5 个授权的折扣数：5 %
   - 6 ~ 10 个授权的折扣数：10 %
   - 大于 10 个授权的折扣数：0 %

3. 试用价：

参考报价

4. 工作频率：

12.156 MHz

5. 面积：

40 K μm^2

6. 工艺：

130 nm

7. 版本：

1.0