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| 4.2V-to-1.2V DC/DC Converter | 参考报价 | 40.000 K μm^2 | 1 MHz | 130 nm |  |
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| The DCDC12 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.05V to 1.3V.An external 10uH inductor is necessary. | 概述 | |||||
| Real-Time-Clock | 参考报价 | 无资料 | 32 KHz | 130 nm | |
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| The RTC is a TSMC 0.13μm Real-Time-Clock cell that provides multiple clocks. This RTC provides an operating voltage range of 2.7V ~ 3.3V, and an operating junction temperature range of -40˚ ~ 125℃. | 概述 | |||||
| 10-Bit 1MSPS Cyclic A/D Converter | 参考报价 | 300.500 K μm^2 | 10.12 Hz | 250 nm | |
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| This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range. The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz | 概述 | |||||
| Chroma Resampler | 参考报价 | 无资料 | 400 MHz | 无资料 | |
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| The IP Core is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colour space. In total, the IP Core package contains two distinct modules – one module that converts from 4:4:4 to 4:2:2 and the other that performs the reciprocal operation from 4:2:2 to 4:4:4. Pixels flow into the design in accordance with the valid ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when PIX_VALID and PIX_READY are both high. At the output interface, pixels and syncs are sampled on a the rising edge of clk when POUT_VALID and POUT_READY are high. The input and output sync signals are coincident with the first pixel of a frame and the first pixel of a line. These are useful to identify the video frame and line boundaries. Application Digital video and image processing Interfacing between different video processing and video transceiver ICs that use different colour formats | 概述 | |||||
| Multi-format Video Deinterlacer | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| The IP Core is a high quality 24-bit RGB video deinterlacer capable of generating progressive output video at up to 4096x4096 pixels in resolution. The design is fully customizable, supporting any desired interlaced video format. The deinterlacer allows for three possible filter algorithms - either BOB, ELA or LCI. All three methods are 'intra-field' methods that perform spatial filtering within the same field. For this reason, the output video is not subject to combing or tearing which is characteristic of a traditional 'weave' approach. Each algorithm has it relative merits in terms of image quality and hardware complexity. In particular, the enhanced LCI algorithm provides excellent all-round performance with reduced image softening and crisp clean edges. Application Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips High-quality video de-interlacing without the overhead of a frame buffer Digital TV set-top boxes and home media solutions | 概述 | |||||
| Video Interlacer | 参考报价 | 无资料 | 500 MHz | 无资料 | |
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| The IP Core is a fully pipelined video interlacer solution that converts any progressive video format into it's interlaced equivalent. Each interlaced output field will have half the number of lines as an input frame. The input and output interfaces are streaming interfaces that follow a simple valid-ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when P_VALID and P_READY are both high. Likewise, output pixels and syncs are sampled on the rising edge of clk when PO_VAL and PO_READY are high. Note that if no flow control is required in the design and the output is guaranteed to accept pixels without stalling, then the signal PO_READY may be tied high and the signal P_READY may be ignored. Application Video solutions for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc. Conversion of all standard and custom video formats such as 1920x1080p to 1920x1080i, 720x480p to 720x480i etc. | 概述 | |||||
| Motion-adaptive Video Deinterlacer | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| The IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216 pixels. The design is fully programmable and supports any desired interlaced video format. The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document. The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3. Application Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips Studio-quality video de-interlacing | 概述 | |||||
| Video Test Pattern Generator | 参考报价 | 无资料 | 500 MHz | 无资料 | |
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| The IP module is a versatile test pattern generator capable of producing a range of test patterns in colour, greyscale and monochrome formats. The module is invaluable in the prototyping stages of digital video systems. In addition, the test pattern generator may be used to provide a blank background display. The video output resolution is controlled by the generic parameters "PPL" and "LPF". The colour, type and dimensions of the test pattern are determined by the parameters INTL, MODE, TYPE and LOG2W. Application Generation of a blank video background Simple screen savers Digital video testing and prototyping | 概述 | |||||
| Video Timing Generator | 参考报价 | 无资料 | 400 MHz | 无资料 | |
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| The IP Core is a fully configurable video timing generator with the ability to support any video resolution up to 216 x 216 pixels in size. The module is compatible with a wide range of video DACs, CODECs and transceivers and provides a flexible solution for displaying digital or analogue video on an external TV, monitor or flat panel display. The module is capable of clock speeds in excess of 400 MHz on some FPGA platforms, making it ideal for the latest generation HD and UHD video solutions. After resynchronizing the input pixels to the pixel-clock domain , the controller locks to the first frame (or field) of video. Once frame-lock is achieved, pixels are supplied on demand to the video timing control unit. This module generates the correct RGB video, sync and blanking information depending on the chosen timing parameters. Application Legacy (SD) and analogue video applications Digital TV and multimedia solutions HD, UHD and SUHD next generation digital video | 概述 | |||||
| RF Power Amplifier Precorrection | 参考报价 | 无资料 | 150 MHz | 无资料 | |
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| The IP is a complete Digital Precorrection(Predistortion) system designed to compensate for the non-linear characteristic of a high-power RF Amplifier. The system is capable of adjusting both the gain and phase of a complex input signal. This is achieved by means of a complex multiplication of the input with a complex polynomial function stored in the LT. The LT contains the inverse PA characteristic and is applied before the amplification stages (either at baseband or IF frequencies). By programming the LT with the inverse gain/phase PA response, the resultant PA response is linearized. After linearization, the output signal is much cleaner with reduced intermodulation distortion. The system may be used in open-loop or closed-loop configuration. For open loop operation, the LUT coefficients are static and programmed during initial setup of the PA precorrection system. For closed-loop operation, an external circuit may compare the baseband inputs and PA outputs and adjust the LUT coefficients dynamically in order to automate the linearization process. Application Precorrection of wide bandwidth signals such as UMTS, WCDMA and OFDM Power amplifier linearization for mobile Base-stations, Broadcasting etc. Precorrection of any type of digitally modulated signal where the signal envelope varies and therefore the instantaneous input power. | 概述 | |||||
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