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| High-speed FIR Filter with symmetry | 参考报价 | 无资料 | 500 MHz | 无资料 |  |
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| This IP is an FIR filter IP Core with symmetrical coefficients and an even or odd number of filter taps. The architecture exploits the symmetry of the coefficients using half the number of multipliers compared to a normal FIR implementation. The result is a filter with a reduced area footprint while still maintaining the capacity for high sample rates. Application High-speed filter applications where resources are limited General purpose FIR filters with symmetrical coefficients | 概述 | |||||
| N-channel multiplexed FIR filter | 参考报价 | 无资料 | 500 MHz | 无资料 | |
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| The IP is an N-channel multiplexed FIR filter designed for high sample rate applications where hardware resources are limited. The main filter core is organized as a scalable systolic array permitting the user to specify large order filters without compromising maximum attainable clock-speed. Essentially the filter functions as if it were 'N' separate FIR filters. Each input sample is multiplexed into the filter at a sample rate equal to Fs /N, where Fs is the sampling frequency of the main filter core. Likewise, output samples are updated at a frequency of Fs /N. The first sample into the filter is aligned by asserting the signal X_VALID high. The signal Y_VALID_val is asserted with the first valid output sample. Data samples are advanced in the pipeline on the rising clock-edge of clk when en is active high. When en is low then all data samples are stalled. The clock-enable signal may be used to temporarily disable the filter - or possibly to modify the effective sampling frequency of the system clock. If the clock-enable is not needed it is recommended that this signal be tied high as it will improve overall circuit performance. Application Dual-channel inputs such as complex valued I/Q in digital communications systems High-speed filtering applications where hardware resources are limited General purpose FIR filters with odd or even numbers of taps | 概述 | |||||
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