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| 进阶物联网开发平台 | 参考报价 | 无资料 | 无资料 | 无资料 |  |
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| This Platform can decrease timing for develop. Single Chip Solution Integrated Gyroscope Sensor Integrated Acceleration Sensor Integrated Communication 32-bit RISC MCU ADC SPI/UART/I2C/GPIO Crypto Engine Easy Integrated Customer’s Logic Applications Security Systems Home and Building Automation IoT | 概述 | |||||
| 金融资讯安全开发平 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This Platform can decrease timing for develop. Single Chip Solution 32-bit RISC MCU SPI/UART/I2C/GPIO Crypto Engine PCIE Gen2/Gen3 USB 2.0 Flash Controller DDR4 Easy Integrated Customer’s Logic Applications Security Network Financial Information Security | 概述 | |||||
| 影音开发平台 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| Single Chip Solution 32-bit RISC MCU SPI/UART/I2C/GPIO Video Process Engine Video DAC/Audio DAC USB 2.0 Video Scaler DDR4 Easy Integrated Customer’s Logic Application DVR and POS DVR ATM machine surveillance Home stay monitoring Multiple channel IP camera | 概述 | |||||
| Digital Down Converter with configurable Decimation Filter | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| DDC is a complex-valued digital down-converter with a configurable number of decimation stages. The design is ideal for high sample-rate applications and permits a digital input signal to be mixed- down and re-sampled at a lower data rate. The DDC is suitable for the down-conversion of any digitally modulated signal to baseband – an essential step before digital processing. The DDC features a high-precision 16-bit DDS oscillator for the digital mixing stage. This oscillator is fully programmable and offers excellent phase and frequency resolution. The digital mixing stage is a complex multiplier that allows the mixing of both real and imaginary (I/Q) inputs. If only real inputs are required, then the imaginary input (q_in) should be tied low. The output decimation stage features a configurable decimate-by-2N poly-phase filter for both I and Q channels. Each filter stage is highly optimized to use only 12 multipliers while still achieving 80 dB of stop-band attenuation. Application Compatible with any digital modulation scheme - e.g. QPSK, BPSK, QAM, WiMAX, WCDMA, COFDM etc. Conversion of IF signals to baseband frequencies for subsequent processing Digital I/Q Demodulators | 概述 | |||||
| 4K/8k capable JPEG Encoder with scalable | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This JPEG compression IP core supports the Baseline Sequential DCT and the Ex- tended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less pow- er than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-MT-V Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame vid- eo. Once programmed, the easy-to-use encoder requires no assistance from a host pro- cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed da- ta, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Stream- ing interface. | 概述 | |||||
| 8/12-bit JPEG decoder for ASIC and FPGA with scalable | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This JPEG decompression IP core supports the Baseline Sequential DCT and Extend- ed Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extreme- ly high pixel rates. The JPEG-ST-V Decoder decompresses JPEG images and the video payload for Mo- tion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-MT-V Encoder Core. This Encoder-Decoder pair pro- vide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro- cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. | 概述 | |||||
| BOSCH CAN 2.0A/B AND CAN FD 1.0 CONTROLLER | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| The CAN controller is an I2C/APB compliant controller to act as a transmitter or receiver in the CAN bus. | 概述 | |||||
| CAN 2.0 & CAN FD Bus Controller Core | 参考报价 | 12.000 K Gates | 无资料 | 无资料 | |
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| The CAN protocol uses a multi-master bus configuration for the transfer of frames be- tween nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between vari- ous components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames. The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It imple- ments a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application | 概述 | |||||
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