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| High-speed FIR Filter with symmetry | 参考报价 | 无资料 | 500 MHz | 无资料 |  |
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| This IP is an FIR filter IP Core with symmetrical coefficients and an even or odd number of filter taps. The architecture exploits the symmetry of the coefficients using half the number of multipliers compared to a normal FIR implementation. The result is a filter with a reduced area footprint while still maintaining the capacity for high sample rates. Application High-speed filter applications where resources are limited General purpose FIR filters with symmetrical coefficients | 概述 | |||||
| N-channel multiplexed FIR filter | 参考报价 | 无资料 | 500 MHz | 无资料 | |
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| The IP is an N-channel multiplexed FIR filter designed for high sample rate applications where hardware resources are limited. The main filter core is organized as a scalable systolic array permitting the user to specify large order filters without compromising maximum attainable clock-speed. Essentially the filter functions as if it were 'N' separate FIR filters. Each input sample is multiplexed into the filter at a sample rate equal to Fs /N, where Fs is the sampling frequency of the main filter core. Likewise, output samples are updated at a frequency of Fs /N. The first sample into the filter is aligned by asserting the signal X_VALID high. The signal Y_VALID_val is asserted with the first valid output sample. Data samples are advanced in the pipeline on the rising clock-edge of clk when en is active high. When en is low then all data samples are stalled. The clock-enable signal may be used to temporarily disable the filter - or possibly to modify the effective sampling frequency of the system clock. If the clock-enable is not needed it is recommended that this signal be tied high as it will improve overall circuit performance. Application Dual-channel inputs such as complex valued I/Q in digital communications systems High-speed filtering applications where hardware resources are limited General purpose FIR filters with odd or even numbers of taps | 概述 | |||||
| FIR filter | 参考报价 | 无资料 | 300 MHz | 无资料 | |
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| FIR_F is an FIR filter implementation designed for very high sample rate applications. Organized as a systolic array the filter is modular and fully scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed. Mathematically, the filter implements the difference equation: y[n] = h0 x[n] + h1 x[n−1] + ... + hN x[n−N ] In the above equation, the input signal is x[n], the output signal is y[n] and h0 to hN represent the filter coefficients. The number N is the filter order, the number of filter taps being equal to N+1. Application General purpose FIR filters with odd or even numbers of taps Filters with arbitrary sets of coefficients Very high-speed filtering applications | 概述 | |||||
| Half-band Nyquist decimation filter | 参考报价 | 无资料 | 300 MHz | 无资料 | |
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| The IP is an N-channel multiplexed FIR filter designed for high sample rate applications where hardware resources are limited. The main filter core is organized as a scalable systolic array permitting the user to specify large order filters without compromising maximum attainable clock-speed. Essentially the filter functions as if it were 'N' separate FIR filters. Each input sample is multiplexed into the filter at a sample rate equal to Fs /N, where Fs is the sampling frequency of the main filter core. Likewise, output samples are updated at a frequency of Fs /N. The first sample into the filter is aligned by asserting the signal X_VALID high. The signal Y_VALID_val is asserted with the first valid output sample. Data samples are advanced in the pipeline on the rising clock-edge of clk when en is active high. When en is low then all data samples are stalled. The clock-enable signal may be used to temporarily disable the filter - or possibly to modify the effective sampling frequency of the system clock. If the clock-enable is not needed it is recommended that this signal be tied high as it will improve overall circuit performance. Application Dual-channel inputs such as complex valued I/Q in digital communications systems High-speed filtering applications where hardware resources are limited General purpose FIR filters with odd or even numbers of taps | 概述 | |||||
| Binary FSK Demodulator | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| This IP is a precision Binary-FSK Demodulator IP Core based on a non-coherent receiver design. The demodulator is fully programmable, allowing for a varied range of symbol rates and mark/space tone frequencies. Input data samples may be either complex or real for support of either passband or baseband signals. The module allows easy connectivity to an external ADC with up to 16-bit signed input samples. Applications: Short range telemetry Software radio | 概述 | |||||
| Binary PSK Demodulator | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| IP is a Binary-PSK demodulator based on a multiply-filter-divide architecture. The design is robust and flexible and allows easy connectivity to an external ADC. As the the carrier recovery circuit is open-loop, there is no feedback path or loop-filter to configure. This results in an extremely simple circuit with a very fast carrier acquisition time. The only requirement is that the user set the desired symbol period and a suitable threshold level for the bit decisions at the symbol decoder. The other design parameters including carrier frequency, symbol rate and sampling frequency should be specified by the user before delivery of the IP Core 1 . The input data samples are 16-bit signed (2's complement) values that are synchronous with the system clock. Input values are sampled on the rising edge of clk when en is high. Application Robust, low bandwidth RF applications for small FPGA devices SRD and ISM band devices Medium to long-range telemetry Software radio | 概述 | |||||
| Precision Tone Decoder | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| The IP is a precision tone decoder with the capacity to support either real or complex data samples. Samples are first mixed-down to baseband before subsequent filtering and tone detection. The centre frequency of the tone is fully programmable and is generated by a local oscillator (DDS). The DDS has an SFDR of better than 80 dBs (with phase dithering) and a theoretical SNR of approximately 100 dBs. After down-conversion, 2 paths are filtered to remove components above the tone of interest. The characteristics of these filters may be changed depending on the desired detection bandwidth and response time. Finally, a power function is used to compute the relative magnitude of the signal after filtering. Application Precision frequency monitoring and control FSK / OOK / ASK demodulation Touch tone decoding (e.g. DTMF tones) Complex digital down conversion | 概述 | |||||
| Periodic waveform generator | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| The IP Core is a high-precision Direct Digital Synthesizer 2 used for the generation of periodic waveforms. On each rising-edge of the sample clock, the phase in the phase accumulator is incremented by the value phase_inc. This phase is quantized to 16-bits and passed as an address to a look-up table which converts the phase into a waveform. In addition to the quadrature outputs sin_out and cos_out, the IP also provides square wave and sawtooth outputs: squ_out and saw_out. All output values are 16-bit signed numbers. Appliaction Digital up/down converters and mixers Versatile waveform generation Digital oscillators Digital modulation | 概述 | |||||
| IIR filter Second-Order | 参考报价 | 无资料 | 150 MHz | 无资料 | |
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| This IP is a second order IIR filter sometimes referred to as a 'bi-quad'. Internally, it has a fully pipelined architecture permitting the highest possible sample rates for IIR filtering. Values are sampled on the rising clock-edge of clk when EN is high. The latency of the IIR filter between the first input sample and the first output sample is 7 clock cycles. Applicaion IIR filtering in higher sample-rate applications General purpose high-pass, band-pass and low-pass filters | 概述 | |||||
| RF Power Amplifier Precorrection | 参考报价 | 无资料 | 150 MHz | 无资料 | |
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| The IP is a complete Digital Precorrection(Predistortion) system designed to compensate for the non-linear characteristic of a high-power RF Amplifier. The system is capable of adjusting both the gain and phase of a complex input signal. This is achieved by means of a complex multiplication of the input with a complex polynomial function stored in the LT. The LT contains the inverse PA characteristic and is applied before the amplification stages (either at baseband or IF frequencies). By programming the LT with the inverse gain/phase PA response, the resultant PA response is linearized. After linearization, the output signal is much cleaner with reduced intermodulation distortion. The system may be used in open-loop or closed-loop configuration. For open loop operation, the LUT coefficients are static and programmed during initial setup of the PA precorrection system. For closed-loop operation, an external circuit may compare the baseband inputs and PA outputs and adjust the LUT coefficients dynamically in order to automate the linearization process. Application Precorrection of wide bandwidth signals such as UMTS, WCDMA and OFDM Power amplifier linearization for mobile Base-stations, Broadcasting etc. Precorrection of any type of digitally modulated signal where the signal envelope varies and therefore the instantaneous input power. | 概述 | |||||
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