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| USB 2.0 ON-THE-GO CONTROLLER | 参考报价 | 75.000 K Gates | 200 MHz | 无资料 |  |
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| This is a universal serial bus (USB) 2.0 On-The-Go (OTG) Controller, which can play dual-role, as a host or a device controller. When it acts as a host, it contains a USB host controller to support all speed transactions. | 概述 | |||||
| 32 bits RISC Microcontroller | 参考报价 | 33.000 K Gates | 100 MHz | 180 nm | |
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| The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces. Applications Wearables IoT Motor Control Appliances Connectivity Smart home/building/enterprice/planet | 概述 | |||||
| AES Codec with 128-bit datapath | 20000 点 | 22.000 K Gates | 260 MHz | 180 nm | |
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| The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed for high throughput applications with optimal logic resources utilization. The encryptor core accepts a 128-bit plaintext input word, and generates a corresponding 128-bit ciphertext output word using a supplied 128, 192, or 256-bit AES key. The decryptor core provides the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The hardware roundkey expansion logic has been designed as a discrete building block. This allows either to build a complete stand-alone AES solution, or to save logic resources by leaving the key generation process to the user. Alternatively, the roundkey expansion logic can be shared between multiple encryption/decryption cores for optimal silicon area resources utilization. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications. | 概述 | |||||
| CAN 2.0 & CAN FD Bus Controller Core | 参考报价 | 12.000 K Gates | 无资料 | 无资料 | |
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| The CAN protocol uses a multi-master bus configuration for the transfer of frames be- tween nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between vari- ous components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames. The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It imple- ments a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application | 概述 | |||||
| BRAINS | 50000 点 | 5.250 K Gates | 1.2 GHz | 40 nm | |
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| With improvement of technology node and IC design is geting more complex, the ratio of embedded memory in SoCs have been exceeding 50%. The fault types of memory are getting complex. The Memory BIST (Built-In Self-Test) is generated for efficient controlling IC cost. The traditional BIST method is inserted along with single memory. If there are many memories in SoCs, the area and testing time of SoCs are expanded a lot due to insertion of BIST. Therefore the SoCs' cost will increase rapidly because memory testing time is too long. We devoted in developing SRAM testing solutions for a long time. BRAINS is based on memory testing patents to reduce testing time and increase yield rate. In addition, BRAINS has many unique features to increase SoCs' reliability and stability. | 概述 | |||||
| HEART(High Efficient Accumulative Repairing Technical) | 50000 点 | 5.250 K Gates | 2.2 GHz | 40 nm | |
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| HEART can efficient repair faulty SRAM after using BRAINS. SoCs can mantain correctness of functions and avoid fatal error of system reault in SRAM's defect through SRAM's repairing technical. HEART is SRAM accumulative repairing technical, and it combines advantages of Soft-repair and Hard-repair. HEART supports internal registers of SoCs and external storages of SoCs to record SRAM's faulty information. Once SoCs have new SRAM's defect after using them for a long time, users can repeated repair SRAM's defect through HEART. In addtion, HEART also support "On-Demad" testing and repairing requirement. It means that users can enable system registers of SoCs or signal of HEART to test and repair SRAM at one when SoCs have fatal error situations. | 概述 | |||||
| NVM test and repair | 60000 点 | 5.250 K Gates | 2.2 GHz | 40 nm | |
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| HEART (High Efficient Accumulative Repairing Technical) is a built-in self-repair (BISR) mechanism which uses to recover errors detected after memory testing and to improve yield rate. This mechanism is implemented with spare memories and a built-in redundancy analyze (BIRA) logics which is designed to allocate the redundancy. It needs a storable device (eFuse, OTP or registers) to store testing results after analysis. We provides an efficient accumulative repairing solution to combine advantages of soft BISR mechanism and hard BISR mechanism for improving yield rate. | 概述 | |||||
| Octal SPI Master/Slave Controller | 参考报价 | 4.641 K Gates | 500 MHz | 无资料 | |
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| Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the most significant bit position in a frame, serial clock phase and polarity are all software- programmable. In master mode the core can control up to 32 slaves. A software controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose | 概述 | |||||
| Configurable Reed Solomon Encoder | 30000 点 | 2.500 K Gates | 250 MHz | 180 nm | |
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| Our IP core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications. | 概述 | |||||
| One Wire Communication | 1200 点 | 1.500 K Gates | 100 MHz | 130 nm | |
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| In some particular application, few pin count but still need chip to chip communication. This IP use one wire bi-direction (open drain) to communication. Just like UART , it is consist of one TX and one RX. User can define their own payload freedomly. All devices are connecting through open-drain pull high bus. Every device can send data to others actively. Waveform Application - Analog IC debug - MCU program port - Low pin count IC | 概述 | |||||
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