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| SPI slave in mode 2 | 1000 点 | 254.000 Gates | 192 MHz | 130 nm |  |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | 概述 | |||||
| Asynchronous I2C Slave | 999 点 | 578.000 Gates | 100 MHz | 130 nm | |
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| Unlike Synchronous type I2C slave design need clock to work. This Asynchronous type don’t need base clock . It is very power saving in some application Application : - Power manager IC - Sensor IC - Software wakeup requirement system | 概述 | |||||
| Clock divider by 3 | 100 点 | 52.000 Gates | 370 MHz | 130 nm | |
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| There are 2 types of circuits in digital logic world. One is combinational, and the other is sequential. The difference between them is that the latter one has storage (memory) while the former one does not. Thus, in contrast to combinational circuits, whose output depends only on the current values of its inputs, the output of sequential circuits depends not only on the current values of its inputs but also on the past values of them. Based on the characteristic of sequential circuits, we can build counters. In addition, we can further build clock dividers with the counters we designed | 概述 | |||||
| 32 bits RISC Microcontroller | 参考报价 | 33.000 K Gates | 100 MHz | 180 nm | |
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| The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces. Applications Wearables IoT Motor Control Appliances Connectivity Smart home/building/enterprice/planet | 概述 | |||||
| 8051 Core | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory. | 概述 | |||||
| UART Serial Interface Controller | 参考报价 | 无资料 | 300 MHz | 无资料 | |
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| UART compatible Serial Interface Controller with receive and transmit FIFOs and support for all standard bit rates from 9600 to 921600 baud. Applications UART Communications RS232, RS422, RS485 etc. Micro-controller interfacing | 概述 | |||||
| I2C Master Serial Interface Controller | 参考报价 | 无资料 | 300 MHz | 无资料 | |
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| Master serial controller compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from ASIC device. Supports standard (100 kbits/s), fast (400 kbits/s) and custom data rates well above 4 Mbits/s. Setup and hold-times on the SDA pin are fully configurable. Applications Inter-chip board-level communications Standard 2-wire comms between a wide range of peripherals, MCUs and COTs ICs | 概述 | |||||
| I2C Slave Serial Interface Controller | 参考报价 | 无资料 | 300 MHz | 无资料 | |
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| Slave serial controller compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your ASIC device via a set of user-defined config and status registers. Supports standard (100 kbits/s), fast (400 kbits/s) and custom rates in excess of 4 Mbits/s. Applications I2C slave communication via your ASIC Inter-chip board-level communications | 概述 | |||||
| DDR4 SDRAM Controller Core | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| Double Data Rate 4 (DDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time. The core supports all new DDR4 features, including: 3DS device configurations, write CRC, data bus inversion (DBI), fine granu-larity refresh, additive latency, per-DRAM addressability, and temperature controlled refresh. | 概述 | |||||
| 8-bit / 16-bit Flash memory controller | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components . Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices. Applications Any application where non-volatile storage is required Offline storage of parameters and data via your Chip | 概述 | |||||
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