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| Chroma Resampler | 参考报价 | 无资料 | 400 MHz | 无资料 |  |
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| The IP Core is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colour space. In total, the IP Core package contains two distinct modules – one module that converts from 4:4:4 to 4:2:2 and the other that performs the reciprocal operation from 4:2:2 to 4:4:4. Pixels flow into the design in accordance with the valid ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when PIX_VALID and PIX_READY are both high. At the output interface, pixels and syncs are sampled on a the rising edge of clk when POUT_VALID and POUT_READY are high. The input and output sync signals are coincident with the first pixel of a frame and the first pixel of a line. These are useful to identify the video frame and line boundaries. Application Digital video and image processing Interfacing between different video processing and video transceiver ICs that use different colour formats | 概述 | |||||
| Multi-format Video Deinterlacer | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| The IP Core is a high quality 24-bit RGB video deinterlacer capable of generating progressive output video at up to 4096x4096 pixels in resolution. The design is fully customizable, supporting any desired interlaced video format. The deinterlacer allows for three possible filter algorithms - either BOB, ELA or LCI. All three methods are 'intra-field' methods that perform spatial filtering within the same field. For this reason, the output video is not subject to combing or tearing which is characteristic of a traditional 'weave' approach. Each algorithm has it relative merits in terms of image quality and hardware complexity. In particular, the enhanced LCI algorithm provides excellent all-round performance with reduced image softening and crisp clean edges. Application Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips High-quality video de-interlacing without the overhead of a frame buffer Digital TV set-top boxes and home media solutions | 概述 | |||||
| Video Interlacer | 参考报价 | 无资料 | 500 MHz | 无资料 | |
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| The IP Core is a fully pipelined video interlacer solution that converts any progressive video format into it's interlaced equivalent. Each interlaced output field will have half the number of lines as an input frame. The input and output interfaces are streaming interfaces that follow a simple valid-ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when P_VALID and P_READY are both high. Likewise, output pixels and syncs are sampled on the rising edge of clk when PO_VAL and PO_READY are high. Note that if no flow control is required in the design and the output is guaranteed to accept pixels without stalling, then the signal PO_READY may be tied high and the signal P_READY may be ignored. Application Video solutions for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc. Conversion of all standard and custom video formats such as 1920x1080p to 1920x1080i, 720x480p to 720x480i etc. | 概述 | |||||
| Motion-adaptive Video Deinterlacer | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| The IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216 pixels. The design is fully programmable and supports any desired interlaced video format. The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document. The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3. Application Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips Studio-quality video de-interlacing | 概述 | |||||
| Video Test Pattern Generator | 参考报价 | 无资料 | 500 MHz | 无资料 | |
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| The IP module is a versatile test pattern generator capable of producing a range of test patterns in colour, greyscale and monochrome formats. The module is invaluable in the prototyping stages of digital video systems. In addition, the test pattern generator may be used to provide a blank background display. The video output resolution is controlled by the generic parameters "PPL" and "LPF". The colour, type and dimensions of the test pattern are determined by the parameters INTL, MODE, TYPE and LOG2W. Application Generation of a blank video background Simple screen savers Digital video testing and prototyping | 概述 | |||||
| Video Timing Generator | 参考报价 | 无资料 | 400 MHz | 无资料 | |
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| The IP Core is a fully configurable video timing generator with the ability to support any video resolution up to 216 x 216 pixels in size. The module is compatible with a wide range of video DACs, CODECs and transceivers and provides a flexible solution for displaying digital or analogue video on an external TV, monitor or flat panel display. The module is capable of clock speeds in excess of 400 MHz on some FPGA platforms, making it ideal for the latest generation HD and UHD video solutions. After resynchronizing the input pixels to the pixel-clock domain , the controller locks to the first frame (or field) of video. Once frame-lock is achieved, pixels are supplied on demand to the video timing control unit. This module generates the correct RGB video, sync and blanking information depending on the chosen timing parameters. Application Legacy (SD) and analogue video applications Digital TV and multimedia solutions HD, UHD and SUHD next generation digital video | 概述 | |||||
| Digital Video overlay module | 参考报价 | 无资料 | 250 MHz | 无资料 | |
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| This IP is a highly versatile video multiplexer that allows one video stream to be inserted over another. By cascading a series of video overlay modules together, any number of video sources may be multiplexed together. The module supports input video streams of any resolution or aspect ratio up to 216 x 216 pixels in size. Video overlay parameters may be changed on a frame-by-frame basis to dynamically change the size and position of the video overlay. Pixels and syncs flow in and out of the video overlay module in accordance with the valid-ready pipeline protocol. The pipeline protocol allows both input and output interfaces to be stalled independently. In addition, the overlay module supports a number of blending operations including an 8-bit alpha channel and bitwise AND, OR and XOR functions. Application Network and Tactical operations centres Digital-video special effects Broadcast TV and film production CCTV and security camera systems | 概述 | |||||
| 2D Graphics Overlay | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| This is a highly versatile on-screen display that allows high-quality anti-aliased bitmap graphics to be inserted over RGB video. The module supports a wide range of graphics effects and the programming interface is very simple to use. The bitmap overlay is partitioned into an array of tiles which are addressed by means of an 8-bit value stored in a 64x64 tile buffer. There are four tile sizes available - either 8x8, 16x16, 32x32 or 64x64. The tiles in the buffer are displayed in a graphics window which may be positioned anywhere within the display area. Bitmaps for each tile are stored in a user-defined ROM which can contain up to 256 different bitmaps stored over three bit-planes. Depending on the chosen graphics mode, the 3-bits per pixel may be used to select one colour from a palette of eight, eight levels of alpha transparency or seven colours on a transparent background. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol. Application Animated 2D graphics including hardware sprites, mouse pointers, cursors , parallax scrolling, moving banners etc. Interactive guides, menus, tables, lists etc. Digital TV and home-media solutions Professional and functional 2D graphic displays and video overlays | 概述 | |||||
| Text Overlay Module | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| The IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video. The module supports a wide range of text effects and the programming interface is very simple. Text is written to a 64x32 character buffer which is mapped (via a bitmap ROM) directly to the display. The characters in the buffer are displayed in a 'TEXT BOX' which may be positioned anywhere in the video display area. Bitmaps for each character are stored in a ROM which may be modified to support different font styles or bitmap graphics. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol. Application Window movement in the same manner as a 2D 'BitBlt' Terminal and Console windows Low cost text and graphics applications Digital TV and home-media solutions | 概述 | |||||
| Bilinear Video Scaling Engine | 参考报价 | 无资料 | 250 MHz | 无资料 | |
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| This IP is a very high quality video scaler capable of generating interpolated output images from 16x16 up to 216 x 216 pixels in resolution. The architecture permits seamless scaling (either up or down) depending on the chosen scale factor. Internally, the scaler uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points. All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics. Pixels flow in and out of the scaling engine in accordance with the valid-ready pipeline protocol.As such, the pipeline protocol allows both input and output interfaces to be stalled independently. The scaler is partitioned into a horizontal scaling section in series with avertical scaling section. Application Conversion of popular video formats to any other resolution such as VGA to XGA, SVGA to HD1080 etc. Picture in Picture (PiP) applications High quality 24-bit RGB/YCbCr video scaling | 概述 | |||||
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