8051 Core |
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The 8051 has gained great popularity since its introduction and is estimated it is
used in a large percentage of all embedded system products.
The basic form of 8051 core includes several on-chip peripherals, like timers and
counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of
on-chip program memory.
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DDR4 SDRAM Controller Core |
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Double Data Rate 4 (DDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time.
The core supports all new DDR4 features, including: 3DS device configurations, write CRC, data bus inversion (DBI), fine granu-larity refresh, additive latency, per-DRAM addressability, and temperature controlled refresh.
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8-bit / 16-bit Flash memory controller |
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FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components . Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices.
Applications
Any application where non-volatile storage is required
Offline storage of parameters and data via your Chip
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车用电子开发平台 |
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Single Chip Solution
Integrated Pressure Sensor
Integrated Acceleration Sensor
Integrated Temperature Sensor
32-bit RISC CPU
PWM
RF Transmitter (300-450 Mhz)
LF Receiver
Easy Integrated Customer’s Logic
Application
Tire Pressure Monitoring System
Automotive electronics
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入门物联网开发平台 |
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This Platform can decrease timing for develop.
Single Chip Solution
Integrated Gyroscope Sensor
Integrated Acceleration Sensor
32-bit RISC CPU
ADC
Wi-Fi/Bluetooth
SPI/UART/I2C/GPIO
Easy Integrated Customer’s Logic
Applications
Home and Building Automation
Smart Energy
Internet of Things
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进阶物联网开发平台 |
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This Platform can decrease timing for develop.
Single Chip Solution
Integrated Gyroscope Sensor
Integrated Acceleration Sensor
Integrated Communication
32-bit RISC MCU
ADC
SPI/UART/I2C/GPIO
Crypto Engine
Easy Integrated Customer’s Logic
Applications
Security Systems
Home and Building Automation
IoT
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概述 |
金融资讯安全开发平 |
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This Platform can decrease timing for develop.
Single Chip Solution
32-bit RISC MCU
SPI/UART/I2C/GPIO
Crypto Engine
PCIE Gen2/Gen3
USB 2.0
Flash Controller
DDR4
Easy Integrated Customer’s Logic
Applications
Security Network
Financial Information Security
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概述 |
影音开发平台 |
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Single Chip Solution
32-bit RISC MCU
SPI/UART/I2C/GPIO
Video Process Engine
Video DAC/Audio DAC
USB 2.0
Video Scaler
DDR4
Easy Integrated Customer’s Logic
Application
DVR and POS DVR
ATM machine surveillance
Home stay monitoring
Multiple channel IP camera
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概述 |
Digital Down Converter with configurable Decimation Filter |
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DDC is a complex-valued digital down-converter with a configurable number of decimation stages. The design is ideal for high sample-rate applications and permits a digital input signal to be mixed-
down and re-sampled at a lower data rate. The DDC is suitable for the down-conversion of any digitally modulated signal to baseband – an essential step before digital processing.
The DDC features a high-precision 16-bit DDS oscillator for the digital mixing stage. This oscillator is fully programmable and offers excellent phase and frequency resolution. The digital mixing stage is a complex multiplier that allows the mixing of both real and imaginary (I/Q) inputs. If only real inputs are required, then the imaginary input (q_in) should be tied low.
The output decimation stage features a configurable decimate-by-2N poly-phase filter for both I and Q channels. Each filter stage is highly optimized to use only 12 multipliers while still achieving 80 dB of stop-band attenuation.
Application
Compatible with any digital modulation scheme - e.g. QPSK, BPSK, QAM, WiMAX, WCDMA, COFDM etc.
Conversion of IF signals to baseband frequencies for subsequent processing
Digital I/Q Demodulators
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概述 |
4K/8k capable JPEG Encoder with scalable |
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This JPEG compression IP core supports the Baseline Sequential DCT and the Ex- tended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less pow- er than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200.
The JPEG-MT-V Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats.
Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame vid- eo.
Once programmed, the easy-to-use encoder requires no assistance from a host pro- cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed da- ta, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Stream- ing interface.
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