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| USB 3.1 GEN1 DUAL-ROLE CONTROLLER | 参考报价 | 无资料 | 30 MHz | 无资料 |  |
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| This is an USB 3.1 Gen1 dual-role controller, which is compliant to USB 2.0/USB 3.1 Gen1 specifications. The controller can act as a standard host or peripheral for easy system implementation. The role can be selected via static pin selection. | 概述 | |||||
| Asynchronous I2C Slave | 999 点 | 578.000 Gates | 100 MHz | 130 nm | |
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| Unlike Synchronous type I2C slave design need clock to work. This Asynchronous type don’t need base clock . It is very power saving in some application Application : - Power manager IC - Sensor IC - Software wakeup requirement system | 概述 | |||||
| One Wire Communication | 1200 点 | 1.500 K Gates | 100 MHz | 130 nm | |
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| In some particular application, few pin count but still need chip to chip communication. This IP use one wire bi-direction (open drain) to communication. Just like UART , it is consist of one TX and one RX. User can define their own payload freedomly. All devices are connecting through open-drain pull high bus. Every device can send data to others actively. Waveform Application - Analog IC debug - MCU program port - Low pin count IC | 概述 | |||||
| 32 bits RISC Microcontroller | 参考报价 | 33.000 K Gates | 100 MHz | 180 nm | |
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| The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces. Applications Wearables IoT Motor Control Appliances Connectivity Smart home/building/enterprice/planet | 概述 | |||||
| 10/100/1000 Ethernet Media Access Controller | 参考报价 | 无资料 | 125 MHz | 130 nm | |
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| The MAC-1G/MAC is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by the IEEE 802.3 standard for media access control over the 10Mbps, 100Mbps and 1Gbps Ethernet. Communication with an external host is implemented via a set of Control and Status Registers and the DMA controller for external shared RAM memory. For data transfers the MAC-1G/MAC operates as a DMA master. It automatically fetches from transmit data buffers and stores receive data buffers into external RAM with minimum CPU intervention. The linked list management enables the use of various memory allocation schemes. There is an interface for external dual port RAMs serving as configurable FIFO memories and there are separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC-1G/MAC from an external host and provides resolution in case of latency of an external bus. Application Network Interface Cards (NICs) Routers, switching hubs | 概述 | |||||
| IIR filter Second-Order | 参考报价 | 无资料 | 150 MHz | 无资料 | |
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| This IP is a second order IIR filter sometimes referred to as a 'bi-quad'. Internally, it has a fully pipelined architecture permitting the highest possible sample rates for IIR filtering. Values are sampled on the rising clock-edge of clk when EN is high. The latency of the IIR filter between the first input sample and the first output sample is 7 clock cycles. Applicaion IIR filtering in higher sample-rate applications General purpose high-pass, band-pass and low-pass filters | 概述 | |||||
| H.264 Encoder IP Core | 参考报价 | 无资料 | 150 MHz | 无资料 | |
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| This H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. The IP offers two encoder variants to meet the different targets of features. The IP include 2 mode. H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes) The IP core is smaller but yields less compression. It does not require external memory. H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile: The IP core is larger but offers a significantly better compression. Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle. The data interfaces in the H.264 Encoder IP Core use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. | 概述 | |||||
| RF Power Amplifier Precorrection | 参考报价 | 无资料 | 150 MHz | 无资料 | |
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| The IP is a complete Digital Precorrection(Predistortion) system designed to compensate for the non-linear characteristic of a high-power RF Amplifier. The system is capable of adjusting both the gain and phase of a complex input signal. This is achieved by means of a complex multiplication of the input with a complex polynomial function stored in the LT. The LT contains the inverse PA characteristic and is applied before the amplification stages (either at baseband or IF frequencies). By programming the LT with the inverse gain/phase PA response, the resultant PA response is linearized. After linearization, the output signal is much cleaner with reduced intermodulation distortion. The system may be used in open-loop or closed-loop configuration. For open loop operation, the LUT coefficients are static and programmed during initial setup of the PA precorrection system. For closed-loop operation, an external circuit may compare the baseband inputs and PA outputs and adjust the LUT coefficients dynamically in order to automate the linearization process. Application Precorrection of wide bandwidth signals such as UMTS, WCDMA and OFDM Power amplifier linearization for mobile Base-stations, Broadcasting etc. Precorrection of any type of digitally modulated signal where the signal envelope varies and therefore the instantaneous input power. | 概述 | |||||
| SPI slave in mode 2 | 1000 点 | 254.000 Gates | 192 MHz | 130 nm | |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | 概述 | |||||
| ITU-R BT.656 video encoder | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| ITU-R_BT is a digital video encoder with integrated colour-space converter. The encoder accepts 24-bit RGB pixels from sequential odd and even fields. These pixels are then mapped to the YCbCr colour-space and formatted correctly into a BT output stream. The output of the encoder generates an industry standard ITU-R BT.656 format video stream together with a video_val signal that is asserted with the first valid byte of the output stream. Applications BT.656 output video generation PAL & NTSC SDTV video format conversion | 概述 | |||||
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