客服
中
心
| Video Frame Buffer | 参考报价 | 无资料 | 300 MHz | 无资料 |  |
|
| VID_FB is a high-speed multi-format video frame buffer that asynchronously samples an input video stream and buffers it in an external memory. Output pixels are read out of the buffer and synchronised to the system clock domain. The VID_FB will automatically adapt to different input and output frame rates. If the input frame rate is too high, then the VID_FB will cleanly drop or 'skip' an input frame. Likewise, if the output frame rate is higher than the input frame rate, then frames will be repeated 3 . The result is a system that seamlessly adapts to the different frame rates at the input and output of the VID_FB. Applications Buffering video frames in external memory Real-time digital video applications Genlocking of multiple video sources | 概述 | |||||
| Color-space Converter | 参考报价 | 无资料 | 400 MHz | 无资料 | |
|
| This IP is a fully pipelined color-space converter that converts pixels between the RGB and YCbCr color spaces. In total, the IP Core package contains two distinct modules – one module that converts from 24-bit RGB to 30-bit 4:4:4 YCbCr and the other that performs the reciprocal operation from 4:4:4 YCbCr to RGB. Application Digital video and image processing | 概述 | |||||
| Video Timing Generator | 参考报价 | 无资料 | 400 MHz | 无资料 | |
|
| The IP Core is a fully configurable video timing generator with the ability to support any video resolution up to 216 x 216 pixels in size. The module is compatible with a wide range of video DACs, CODECs and transceivers and provides a flexible solution for displaying digital or analogue video on an external TV, monitor or flat panel display. The module is capable of clock speeds in excess of 400 MHz on some FPGA platforms, making it ideal for the latest generation HD and UHD video solutions. After resynchronizing the input pixels to the pixel-clock domain , the controller locks to the first frame (or field) of video. Once frame-lock is achieved, pixels are supplied on demand to the video timing control unit. This module generates the correct RGB video, sync and blanking information depending on the chosen timing parameters. Application Legacy (SD) and analogue video applications Digital TV and multimedia solutions HD, UHD and SUHD next generation digital video | 概述 | |||||
| Chroma Resampler | 参考报价 | 无资料 | 400 MHz | 无资料 | |
|
| The IP Core is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colour space. In total, the IP Core package contains two distinct modules – one module that converts from 4:4:4 to 4:2:2 and the other that performs the reciprocal operation from 4:2:2 to 4:4:4. Pixels flow into the design in accordance with the valid ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when PIX_VALID and PIX_READY are both high. At the output interface, pixels and syncs are sampled on a the rising edge of clk when POUT_VALID and POUT_READY are high. The input and output sync signals are coincident with the first pixel of a frame and the first pixel of a line. These are useful to identify the video frame and line boundaries. Application Digital video and image processing Interfacing between different video processing and video transceiver ICs that use different colour formats | 概述 | |||||
| Video Test Pattern Generator | 参考报价 | 无资料 | 500 MHz | 无资料 | |
|
| The IP module is a versatile test pattern generator capable of producing a range of test patterns in colour, greyscale and monochrome formats. The module is invaluable in the prototyping stages of digital video systems. In addition, the test pattern generator may be used to provide a blank background display. The video output resolution is controlled by the generic parameters "PPL" and "LPF". The colour, type and dimensions of the test pattern are determined by the parameters INTL, MODE, TYPE and LOG2W. Application Generation of a blank video background Simple screen savers Digital video testing and prototyping | 概述 | |||||
| Video Interlacer | 参考报价 | 无资料 | 500 MHz | 无资料 | |
|
| The IP Core is a fully pipelined video interlacer solution that converts any progressive video format into it's interlaced equivalent. Each interlaced output field will have half the number of lines as an input frame. The input and output interfaces are streaming interfaces that follow a simple valid-ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when P_VALID and P_READY are both high. Likewise, output pixels and syncs are sampled on the rising edge of clk when PO_VAL and PO_READY are high. Note that if no flow control is required in the design and the output is guaranteed to accept pixels without stalling, then the signal PO_READY may be tied high and the signal P_READY may be ignored. Application Video solutions for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc. Conversion of all standard and custom video formats such as 1920x1080p to 1920x1080i, 720x480p to 720x480i etc. | 概述 | |||||
| 微IP | 价格 | 逻辑闸数 | 工作频率 | 工艺 | 评价 | |
|---|---|---|---|---|---|---|