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| The TDM-Rx-Pro is part of proven audio interface cores featuring a configurable multi-channel audio | 参考报价 | 无资料 | 192 KHz | 65 nm |  |
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| The TDM-Rx-Pro is part of proven audio interface cores featuring a configurable multi-channel audio interface designed to input serial (TDM) digital audio streams from various manufacturers. The TDM-Rx-Pro front-end also supports the well known stereo formats: Philips I2S, Left-Justified or Right-Justified. The TDM-Rx-Pro backend is supplied with a choice of AMBA®, CoreConnect™ or a flexible parallel interface. | 概述 | |||||
| ASRC-Lite : 16-bit -90dB THD+N Multi-Channel Audio Sample | 参考报价 | 无资料 | 192 KHz | 45 nm | |
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| The ASRC-lite is part of multi-channel asynchronous Audio Sample Rate Converter (ASRC). This core can be used to interface digital audio equipments operating at different sample rates. It has been designed for systems that require a low-cost solution, maintaining low harmonic distortion and noise, and a high tolerance and rejection of input jitter. The ASRC-lite can perform common sample rate conversions with less than -90 dB of Total Harmonic Distortion plus Noise (THD+N) and has a Dynamic range of 92 dB, supporting input data of 16-bit resolution. The ASRC series are implemented to support several key industry interfaces: TDM parallel, TDM serial, Parallel, I2S, SPDIF-AES3. We offers a broad range of asynchronous sample rate converters targeted for variety of audio applications Application : Set-top boxes, professional and hi-fi audio Home Theater Systems Automotive Audio Systems Digital Audio Effects Processors Digital Audio Broadcast Equipment | 概述 | |||||
| ASRC-Pro : 24-bit -130dB THD+N Multi-Channel Audio Sample Rate Converter | 参考报价 | 无资料 | 8.192 MHz | 45 nm | |
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| The ASRC-pro is part of multi-channel Asynchronous Audio Sample Rate Converters (ASRC). This core can be used to interface digital audio equipments operating at different sample rates. It has been designed for systems requiring very high quality in terms of low harmonic distortion and noise, tolerance and rejection of input jitter. The ASRC-pro can perform common sample rate conversions with less than -130 dB of Total Harmonic Distortion plus Noise (THD+N) and has a Dynamic range of 131 dB, supporting input data processing of up to 24-bit resolution. The ASRC series are implemented to support several key industry interfaces: TDM parallel, TDM serial, Parallel, I2S, SPDIF-AES3. We offers a broad range of asynchronous sample rate converters targeted for variety of audio applications. Application: Set-top boxes, professional and hi-fi audio Home Theater Systems Automotive Audio Systems Digital Audio Effects Processors Digital Audio Broadcast Equipment | 概述 | |||||
| 8/12-bit JPEG decoder for ASIC and FPGA with scalable | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This JPEG decompression IP core supports the Baseline Sequential DCT and Extend- ed Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extreme- ly high pixel rates. The JPEG-ST-V Decoder decompresses JPEG images and the video payload for Mo- tion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-MT-V Encoder Core. This Encoder-Decoder pair pro- vide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro- cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. | 概述 | |||||
| 4K/8k capable JPEG Encoder with scalable | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| This JPEG compression IP core supports the Baseline Sequential DCT and the Ex- tended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less pow- er than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-MT-V Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame vid- eo. Once programmed, the easy-to-use encoder requires no assistance from a host pro- cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed da- ta, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Stream- ing interface. | 概述 | |||||
| Chroma Resampler | 参考报价 | 无资料 | 400 MHz | 无资料 | |
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| The IP Core is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colour space. In total, the IP Core package contains two distinct modules – one module that converts from 4:4:4 to 4:2:2 and the other that performs the reciprocal operation from 4:2:2 to 4:4:4. Pixels flow into the design in accordance with the valid ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when PIX_VALID and PIX_READY are both high. At the output interface, pixels and syncs are sampled on a the rising edge of clk when POUT_VALID and POUT_READY are high. The input and output sync signals are coincident with the first pixel of a frame and the first pixel of a line. These are useful to identify the video frame and line boundaries. Application Digital video and image processing Interfacing between different video processing and video transceiver ICs that use different colour formats | 概述 | |||||
| Multi-format Video Deinterlacer | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| The IP Core is a high quality 24-bit RGB video deinterlacer capable of generating progressive output video at up to 4096x4096 pixels in resolution. The design is fully customizable, supporting any desired interlaced video format. The deinterlacer allows for three possible filter algorithms - either BOB, ELA or LCI. All three methods are 'intra-field' methods that perform spatial filtering within the same field. For this reason, the output video is not subject to combing or tearing which is characteristic of a traditional 'weave' approach. Each algorithm has it relative merits in terms of image quality and hardware complexity. In particular, the enhanced LCI algorithm provides excellent all-round performance with reduced image softening and crisp clean edges. Application Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips High-quality video de-interlacing without the overhead of a frame buffer Digital TV set-top boxes and home media solutions | 概述 | |||||
| Video Interlacer | 参考报价 | 无资料 | 500 MHz | 无资料 | |
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| The IP Core is a fully pipelined video interlacer solution that converts any progressive video format into it's interlaced equivalent. Each interlaced output field will have half the number of lines as an input frame. The input and output interfaces are streaming interfaces that follow a simple valid-ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when P_VALID and P_READY are both high. Likewise, output pixels and syncs are sampled on the rising edge of clk when PO_VAL and PO_READY are high. Note that if no flow control is required in the design and the output is guaranteed to accept pixels without stalling, then the signal PO_READY may be tied high and the signal P_READY may be ignored. Application Video solutions for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc. Conversion of all standard and custom video formats such as 1920x1080p to 1920x1080i, 720x480p to 720x480i etc. | 概述 | |||||
| Motion-adaptive Video Deinterlacer | 参考报价 | 无资料 | 200 MHz | 无资料 | |
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| The IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216 pixels. The design is fully programmable and supports any desired interlaced video format. The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document. The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3. Application Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips Studio-quality video de-interlacing | 概述 | |||||
| Video Test Pattern Generator | 参考报价 | 无资料 | 500 MHz | 无资料 | |
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| The IP module is a versatile test pattern generator capable of producing a range of test patterns in colour, greyscale and monochrome formats. The module is invaluable in the prototyping stages of digital video systems. In addition, the test pattern generator may be used to provide a blank background display. The video output resolution is controlled by the generic parameters "PPL" and "LPF". The colour, type and dimensions of the test pattern are determined by the parameters INTL, MODE, TYPE and LOG2W. Application Generation of a blank video background Simple screen savers Digital video testing and prototyping | 概述 | |||||
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