Contact Us   客
   服
   中
   心










商城 > IP 商城

    
8-bit / 16-bit Flash memory controller 参考报价 无资料 无资料 无资料  
FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components . Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices.  Applications Any application where non-volatile storage is required Offline storage of parameters and data via your Chip     概述
NVM test and repair 60000 点 5.250 K Gates 2.2 GHz 40 nm  
HEART (High Efficient Accumulative Repairing Technical) is a built-in self-repair (BISR) mechanism which uses to recover errors detected after memory testing and to improve yield rate. This mechanism is implemented with spare memories and a built-in redundancy analyze (BIRA) logics which is designed to allocate the redundancy. It needs a storable device (eFuse, OTP or registers) to store testing results after analysis. We provides an efficient accumulative repairing solution to combine advantages of soft BISR mechanism and hard BISR mechanism for improving yield rate. 概述
HEART(High Efficient Accumulative Repairing Technical) 50000 点 5.250 K Gates 2.2 GHz 40 nm  
HEART can efficient repair faulty SRAM after using BRAINS. SoCs can mantain correctness of functions and avoid fatal error of system reault in SRAM's defect through SRAM's repairing technical. HEART is SRAM accumulative repairing technical, and it combines advantages of Soft-repair and Hard-repair. HEART supports internal registers of SoCs and external storages of SoCs to record SRAM's faulty information. Once SoCs have new SRAM's defect after using them for a long time, users can repeated repair SRAM's defect through HEART. In addtion, HEART also support "On-Demad" testing and repairing requirement. It means that users can enable system registers of SoCs or signal of HEART to test and repair SRAM at one when SoCs have fatal error situations.   概述
BRAINS 50000 点 5.250 K Gates 1.2 GHz 40 nm  
With improvement of technology node and IC design is geting more complex, the ratio of embedded memory in SoCs have been exceeding 50%. The fault types of memory are getting complex. The Memory BIST (Built-In Self-Test) is generated for efficient controlling IC cost. The traditional BIST method is inserted along with single memory. If there are many memories in SoCs, the area and testing time of SoCs are expanded a lot due to insertion of BIST. Therefore the SoCs' cost will increase rapidly because memory testing time is too long.  We devoted in developing SRAM testing solutions for a long time. BRAINS is based on memory testing patents to reduce testing time and increase yield rate. In addition, BRAINS has many unique features to increase SoCs' reliability and stability.   概述
微IP 价格 逻辑闸数 工作频率 工艺   评价