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| ITU-R BT.656 video decoder | 参考报价 | 无资料 | 300 Hz | 无资料 |  |
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| DEC_BT656 is a digital video decoder with integrated colour-space converter. It's function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent processing. Pixels are extracted from the BT.656 input stream and converted to RGB888 format. Application BT.656 input video capture and processing PAL & NTSC SDTV interlaced format conversion | 概述 | |||||
| Rapid IO PHY in 65nm | 参考报价 | 2.295 μm^2 | 25 Hz | 65 nm | |
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| The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). | 概述 | |||||
| USB 3.0 PHY in 110nm | 参考报价 | 1.000 M μm^2 | 25 Hz | 110 nm | |
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| The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification. This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. | 概述 | |||||
| 10-Bit 1MSPS Cyclic A/D Converter | 参考报价 | 300.500 K μm^2 | 10.12 Hz | 250 nm | |
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| This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range. The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz | 概述 | |||||
| 4.2V-to-1.8V DC/DC Converte | 参考报价 | 40.000 K μm^2 | 1 Hz | 130 nm | |
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| The DCDC18 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.65V to 1.9V.An external 10uH inductor is necessary. | 概述 | |||||
| 电流式感测器尿酸浓度检测 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| 本电路为低功耗之电流输入电流输出，能感测的电流范围因输入端为低阻抗的关系，能量测的电流范围能从250pA~50uA。本电路共有48颗MOS，其中包含一个辅导放大器(OTA)、自体偏压放大器(OPA)与9颗低功率MOS，运用电流镜架构把输入电流复制到输出端，电路稳定度也不会随着溶液之等效阻抗而明显变动，使其能更稳定运作。利用电化学的安培法来量测葡萄糖氧化反应所产生的电流信号，输入电流式读出电路，做电流讯号处理，后端再以微控器处理电路输出讯号，并做数值的转换，转换成血糖值，最后显示在LCD上，完成一血糖机雏形。 应用领域: 血糖 尿酸 胆固醇 酒精浓度 专利取得 : 美国 中华民国 | 概述 | |||||
| 8051 Core | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory. | 概述 | |||||
| DDR4 SDRAM Controller Core | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| Double Data Rate 4 (DDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time. The core supports all new DDR4 features, including: 3DS device configurations, write CRC, data bus inversion (DBI), fine granu-larity refresh, additive latency, per-DRAM addressability, and temperature controlled refresh. | 概述 | |||||
| 8-bit / 16-bit Flash memory controller | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components . Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices. Applications Any application where non-volatile storage is required Offline storage of parameters and data via your Chip | 概述 | |||||
| 车用电子开发平台 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| Single Chip Solution Integrated Pressure Sensor Integrated Acceleration Sensor Integrated Temperature Sensor 32-bit RISC CPU PWM RF Transmitter (300-450 Mhz) LF Receiver Easy Integrated Customer’s Logic Application Tire Pressure Monitoring System Automotive electronics | 概述 | |||||
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