Asynchronous I2C Slave |
999 点 |
578.000 Gates |
100 MHz |
130 nm |
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Unlike Synchronous type I2C slave design need clock to work. This Asynchronous type don’t need base clock . It is very power saving in some application
Application :
- Power manager IC
- Sensor IC
- Software wakeup requirement system
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概述 |
One Wire Communication |
1200 点 |
1.500 K Gates |
100 MHz |
130 nm |
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In some particular application, few pin count but still need chip to chip communication. This IP use one wire bi-direction (open drain) to communication. Just like UART , it is consist of one TX and one RX. User can define their own payload freedomly.
All devices are connecting through open-drain pull high bus. Every device can send data to others actively.
Waveform
Application
- Analog IC debug
- MCU program port
- Low pin count IC
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概述 |
32 bits RISC Microcontroller |
参考报价 |
33.000 K Gates |
100 MHz |
180 nm |
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The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces.
Applications
Wearables
IoT
Motor Control
Appliances
Connectivity
Smart home/building/enterprice/planet
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概述 |
10-bit 80 MSPS ADC IP in 130 nm |
60000 点 |
210.000 K μm^2 |
80 MHz |
130 nm |
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UIP_ADC10_80M_156287 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.
The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.
The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.
UIP_ADC10_80M_156287 can be used in the following applications:
‧Digital imaging
‧TV/Video
‧Wireless LAN
‧Rx communication channel
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概述 |
[110nm]10-bit 80 MSPS ADC IP |
60000 点 |
210.000 K μm^2 |
80 MHz |
110 nm |
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UIP_ADC10_80M_183288 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.
The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.
The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.
UIP_ADC10_80M_183288 can be used in the following applications:
‧Digital imaging
‧TV/Video
‧Wireless LAN
‧Rx communication channel
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概述 |
12-Bit 50 MSPS ADC in IBM 180 SOI |
参考报价 |
280.000 μm^2 |
50 MHz |
180 nm |
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MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area.
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概述 |
PLL 1300M UMC 28 nm logic and Mixed-Mode HPC process |
参考报价 |
109.850 K μm^2 |
50 MHz |
28 nm |
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It is used to generate a stable, high-speed clock from an external slower clock signal. It integrates one Voltage-Controlled Oscillator (VCO), one Phase-Frequency Detector (PFD), one Low-Pass Filter (LPF), one 8-bit programmable divider, and other associated support circuitries. This PLL supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. This IP uses the input operating frequency of PFD ranging from 6 MHz to 25 MHz and generates the output frequency ranging from 25 MHz to 1300 MHz.
The jitter performance of a PLL is highly dependent on the floor plan of ASIC. Because PLL is a sensitive cell when integrated into an ASIC design, the best way to maximize its capacity is to keep PLL away from the noisy blocks in the core region, such as the memory block and the high-driving logic circuit, and the I/O region, such as the high-driving I/O. This PLL must be placed around the I/O area. Providing sufficient space between this PLL and the noisy blocks is a simple and effective approach to reduce the coupled substrate noise.
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概述 |
USB2.0 OTG PHY in 40 nm |
80000 点 |
257.556 K μm^2 |
30.6 MHz |
40 nm |
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The IP is an UTMI+ Level 3 compatible USB2.0 OTG function
transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis
comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel
data for high speed and full speed. It is also support full speed and low speed
serial mode.
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概述 |
USB2.0 UTMI Device PHY(non-oscillator) |
100000 点 |
280.000 K μm^2 |
30.6 MHz |
40 nm |
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The USB PHY is an UTMI compatible USB2.0 device PHY IP which does not
require external oscillator reference. It is comprised of both USB1.1 and USB2.0
transceivers and it is also comprised of digital logic needed to convert USB serial
data to 8 or 16 bit parallel data.
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概述 |
USB 3.1 GEN1 DUAL-ROLE CONTROLLER |
参考报价 |
无资料 |
30 MHz |
无资料 |
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This is an USB 3.1 Gen1 dual-role controller, which is compliant to USB 2.0/USB 3.1 Gen1 specifications. The controller can act as a standard
host or peripheral for easy system implementation. The role can be selected via static pin selection.
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概述 |