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| 12-Bit 800KSPS Low Power SAR-ADC | 参考报价 | 无资料 | 25 MHz | 180 nm |  |
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| The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. | 概述 | |||||
| 8-Bit 7 GSPS SAR ADC | 参考报价 | 300.000 K μm^2 | 7 GHz | 16 nm | |
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| This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area. APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition | 概述 | |||||
| 电流式感测器尿酸浓度检测 | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| 本电路为低功耗之电流输入电流输出，能感测的电流范围因输入端为低阻抗的关系，能量测的电流范围能从250pA~50uA。本电路共有48颗MOS，其中包含一个辅导放大器(OTA)、自体偏压放大器(OPA)与9颗低功率MOS，运用电流镜架构把输入电流复制到输出端，电路稳定度也不会随着溶液之等效阻抗而明显变动，使其能更稳定运作。利用电化学的安培法来量测葡萄糖氧化反应所产生的电流信号，输入电流式读出电路，做电流讯号处理，后端再以微控器处理电路输出讯号，并做数值的转换，转换成血糖值，最后显示在LCD上，完成一血糖机雏形。 应用领域: 血糖 尿酸 胆固醇 酒精浓度 专利取得 : 美国 中华民国 | 概述 | |||||
| 32 bits RISC Microcontroller | 参考报价 | 33.000 K Gates | 100 MHz | 180 nm | |
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| The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces. Applications Wearables IoT Motor Control Appliances Connectivity Smart home/building/enterprice/planet | 概述 | |||||
| 8051 Core | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory. | 概述 | |||||
| UART Serial Interface Controller | 参考报价 | 无资料 | 300 MHz | 无资料 | |
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| UART compatible Serial Interface Controller with receive and transmit FIFOs and support for all standard bit rates from 9600 to 921600 baud. Applications UART Communications RS232, RS422, RS485 etc. Micro-controller interfacing | 概述 | |||||
| I2C Master Serial Interface Controller | 参考报价 | 无资料 | 300 MHz | 无资料 | |
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| Master serial controller compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from ASIC device. Supports standard (100 kbits/s), fast (400 kbits/s) and custom data rates well above 4 Mbits/s. Setup and hold-times on the SDA pin are fully configurable. Applications Inter-chip board-level communications Standard 2-wire comms between a wide range of peripherals, MCUs and COTs ICs | 概述 | |||||
| I2C Slave Serial Interface Controller | 参考报价 | 无资料 | 300 MHz | 无资料 | |
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| Slave serial controller compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your ASIC device via a set of user-defined config and status registers. Supports standard (100 kbits/s), fast (400 kbits/s) and custom rates in excess of 4 Mbits/s. Applications I2C slave communication via your ASIC Inter-chip board-level communications | 概述 | |||||
| DDR4 SDRAM Controller Core | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| Double Data Rate 4 (DDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time. The core supports all new DDR4 features, including: 3DS device configurations, write CRC, data bus inversion (DBI), fine granu-larity refresh, additive latency, per-DRAM addressability, and temperature controlled refresh. | 概述 | |||||
| 8-bit / 16-bit Flash memory controller | 参考报价 | 无资料 | 无资料 | 无资料 | |
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| FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components . Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices. Applications Any application where non-volatile storage is required Offline storage of parameters and data via your Chip | 概述 | |||||
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