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2.4G PLL(UMC 28nm HPC) 参考报价 24.000 K μm^2 2.4 GHz 28 nm  
Clock output 2.4GHz Input clock 10 ~ 50MHz Current consumption: < 4mA Supply: 1.8V / 0.9V UMC 28nm HPC 概述
PLL with Multiple Output Frequency 参考报价 40.000 K μm^2 12.156 MHz 130 nm  
The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source.  This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider.   This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃.  概述
PLL 800M UMC 28 nm logic and Mixed-Mode HPC process 参考报价 230.000 μm^2 800 MHz 28 nm  
It is a 28-nm low-power spread spectrum clock generator that supports an operating frequency ranging from 400 MHz to 800 MHz and from 200 MHz to 400 MHz. This SSCG is programmable to perform the frequency synthesis and spread-spectrum function for the Electro Magnetic Interference (EMI) reduction in various ASIC designs. 概述
PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process 参考报价 270.000 μm^2 1.6 GHz 28 nm  
A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz. This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate a high-speed clock. The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz. 概述
PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process 参考报价 230.000 μm^2 2 GHz 28 nm  
A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate an accurate clock.  概述
PLL 1300M UMC 28 nm logic and Mixed-Mode HPC process 参考报价 109.850 K μm^2 50 MHz 28 nm  
It is used to generate a stable, high-speed clock from an external slower clock signal. It integrates one Voltage-Controlled Oscillator (VCO), one Phase-Frequency Detector (PFD), one Low-Pass Filter (LPF), one 8-bit programmable divider, and other associated support circuitries. This PLL supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. This IP uses the input operating frequency of PFD ranging from 6 MHz to 25 MHz and generates the output frequency ranging from 25 MHz to 1300 MHz.    The jitter performance of a PLL is highly dependent on the floor plan of ASIC. Because PLL is a sensitive cell when integrated into an ASIC design, the best way to maximize its capacity is to keep PLL away from the noisy blocks in the core region, such as the memory block and the high-driving logic circuit, and the I/O region, such as the high-driving I/O. This PLL must be placed around the I/O area. Providing sufficient space between this PLL and the noisy blocks is a simple and effective approach to reduce the coupled substrate noise.   概述
PLL 3000M UMC 28 nm logic and Mixed-Mode HPC process 参考报价 92.400 K μm^2 27 MHz 28 nm  
It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz. 概述
WiFi Frequency Synthesizer IP In 2.4GHz Band 100000 点 200.000 K μm^2 3.2 GHz 55 nm  
The frequency  synthesizer  uses  a  single  1.25V  power supply.  Good  noise  immunity  allows  this  IP  to  be integrated  in  a  noisy  SOC environment.  The  synthesizer  operates  at  1.5X  WiFi  2.4GHz  band  for  wireless application.  概述
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