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| One Wire Communication | 1200 点 | 1.500 K Gates | 100 MHz | 130 nm |  |
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| In some particular application, few pin count but still need chip to chip communication. This IP use one wire bi-direction (open drain) to communication. Just like UART , it is consist of one TX and one RX. User can define their own payload freedomly. All devices are connecting through open-drain pull high bus. Every device can send data to others actively. Waveform Application - Analog IC debug - MCU program port - Low pin count IC | 概述 | |||||
| Low power oscillator | 12000 点 | 100.100 μm^2 | 32 KHz | 40 nm | |
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| OSC32K is designed for 40nm advance process with 1.2v to 3.3v wide power(VDD) range. | 概述 | |||||
| AES Codec with 8-bit datapath | 20000 点 | 1.300 K Gates | 515 MHz | 180 nm | |
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| The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed to require minimum logic resources rendering it an ideal solution for low power applications. This has been achieved by using an 8-bit data path size which means that 16 clock cycles are required to load/unload the 128-bit plaintext/ciphertext block. The encryptor receives the 128-bit plaintext block in 8-bit input symbols and generates the corresponding 128-bit ciphertext block in 8-bit output symbols using a supplied 128, 192, or 256-bit AES key. The pre-computed key values are read from an internal round key RAM. A key expander module is provided as an optional module to allow automatic generation and loading of the round key RAM. The decryptor implements the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications. | 概述 | |||||
| AES Codec with 128-bit datapath | 20000 点 | 22.000 K Gates | 260 MHz | 180 nm | |
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| The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed for high throughput applications with optimal logic resources utilization. The encryptor core accepts a 128-bit plaintext input word, and generates a corresponding 128-bit ciphertext output word using a supplied 128, 192, or 256-bit AES key. The decryptor core provides the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The hardware roundkey expansion logic has been designed as a discrete building block. This allows either to build a complete stand-alone AES solution, or to save logic resources by leaving the key generation process to the user. Alternatively, the roundkey expansion logic can be shared between multiple encryption/decryption cores for optimal silicon area resources utilization. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications. | 概述 | |||||
| Configurable Reed Solomon Encoder | 30000 点 | 2.500 K Gates | 250 MHz | 180 nm | |
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| Our IP core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications. | 概述 | |||||
| BRAINS | 50000 点 | 5.250 K Gates | 1.2 GHz | 40 nm | |
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| With improvement of technology node and IC design is geting more complex, the ratio of embedded memory in SoCs have been exceeding 50%. The fault types of memory are getting complex. The Memory BIST (Built-In Self-Test) is generated for efficient controlling IC cost. The traditional BIST method is inserted along with single memory. If there are many memories in SoCs, the area and testing time of SoCs are expanded a lot due to insertion of BIST. Therefore the SoCs' cost will increase rapidly because memory testing time is too long. We devoted in developing SRAM testing solutions for a long time. BRAINS is based on memory testing patents to reduce testing time and increase yield rate. In addition, BRAINS has many unique features to increase SoCs' reliability and stability. | 概述 | |||||
| HEART(High Efficient Accumulative Repairing Technical) | 50000 点 | 5.250 K Gates | 2.2 GHz | 40 nm | |
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| HEART can efficient repair faulty SRAM after using BRAINS. SoCs can mantain correctness of functions and avoid fatal error of system reault in SRAM's defect through SRAM's repairing technical. HEART is SRAM accumulative repairing technical, and it combines advantages of Soft-repair and Hard-repair. HEART supports internal registers of SoCs and external storages of SoCs to record SRAM's faulty information. Once SoCs have new SRAM's defect after using them for a long time, users can repeated repair SRAM's defect through HEART. In addtion, HEART also support "On-Demad" testing and repairing requirement. It means that users can enable system registers of SoCs or signal of HEART to test and repair SRAM at one when SoCs have fatal error situations. | 概述 | |||||
| 10-bit 300 MSPS Video DAC IP in 90 nm | 60000 点 | 76.000 K μm^2 | 300 MHz | 90 nm | |
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| The UIP_DAC10-300M_205370 is a 10-bit DAC designed in low power TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2V, in unsigned format. A 3.3V supply is used for the analog portion of the IP. This high performance DAC is designed for CVBS standard or RGB Video signal bandwidth. The IP consumes only 41 mA at 300 MSPS operation and utilizes a silicon area of only 0.076 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The DAC output current is 6-bit programmable. The IP architecture is robust and can be ported to other 90 nm processes. APPLICATIONS Composite Video (CVBS) HDTV RGB Video DAC Output Model | 概述 | |||||
| 10-bit 80 MSPS ADC IP in 130 nm | 60000 点 | 210.000 K μm^2 | 80 MHz | 130 nm | |
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| UIP_ADC10_80M_156287 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_80M_156287 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel | 概述 | |||||
| [110nm]10-bit 80 MSPS ADC IP | 60000 点 | 210.000 K μm^2 | 80 MHz | 110 nm | |
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| UIP_ADC10_80M_183288 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_80M_183288 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel | 概述 | |||||
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