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| 14-Bit 3 MSPS ADC in GSMC110nm | 60000 点 | 32.000 K μm^2 | 3 MHz | 110 nm |  |
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| UIP_ADC14_3M_245303 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low power and small area. The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. This ADC consumes 150 uA at 3 MSPS operation and occupies silicon area of 0.32 mm2 . The ADC has high immunity to substrate noise and is ideal for SoC integration. APPLICATIONS General purpose data acquisition Battery monitory system Temperature monitory system | 概述 | |||||
| 14 Bit Rail to Rail DAC | 60000 点 | 75.000 K μm^2 | 1 MHz | 110 nm | |
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| UIP_DAC14_1M_392231 is compact and low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from 1.7V to 5.6V. Its single-end output ranges from 0.1 to 0.9 of supply voltage. This DAC IP is self-biased and optimized for low power and small area. At 1 MHz conversation rate, it only consumes 680uA to drive 15K/50pF loading and occupies silicon area of 0.075 mm2. APPLICATIONS General purpose digital to analog converter Battery monitory system Housekeeping Auxiliary functionality | 概述 | |||||
| NVM test and repair | 60000 点 | 5.250 K Gates | 2.2 GHz | 40 nm | |
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| HEART (High Efficient Accumulative Repairing Technical) is a built-in self-repair (BISR) mechanism which uses to recover errors detected after memory testing and to improve yield rate. This mechanism is implemented with spare memories and a built-in redundancy analyze (BIRA) logics which is designed to allocate the redundancy. It needs a storable device (eFuse, OTP or registers) to store testing results after analysis. We provides an efficient accumulative repairing solution to combine advantages of soft BISR mechanism and hard BISR mechanism for improving yield rate. | 概述 | |||||
| 10-bit 165 MSPS ADC IP in 130 nm | 70000 点 | 210.000 K μm^2 | 165 MHz | 130 nm | |
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| UIP_ADC10_165M_166413 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_166413 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT | 概述 | |||||
| [110nm] 10-bit 165 MSPS ADC IP | 70000 点 | 210.000 K μm^2 | 165 MHz | 110 nm | |
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| UIP_ADC10_165M_213779 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_213779 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT | 概述 | |||||
| 12-Bit 320MPS IQ DAC in TSMC40LP | 70000 点 | 250.000 K μm^2 | 320 MHz | 180 nm | |
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| UIP_DAC12X2_320M_922687 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. This IQ DAC IP is optimized for low power and small area. At 320 MHz conversation rate, it only consumes 63mW and occupies silicon area of 0.25 mm2. APPLICATIONS WiFi / LTE / WiMax Wireless MIMO Digital Video Communication Transmit | 概述 | |||||
| 10-bit 165 MSPS ADC IP in 28 nm | 80000 点 | 70.000 K μm^2 | 165 MHz | 28 nm | |
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| UIP_ADC10_165M_564144 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm^2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_564144 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel | 概述 | |||||
| 10-bit 165 MSPS ADC IP in 28 nm | 80000 点 | 70.000 K μm^2 | 165 MHz | 28 nm | |
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| UIP_ADC10_165M_809744 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_809744 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT | 概述 | |||||
| USB2.0 OTG PHY in 40 nm | 80000 点 | 257.556 K μm^2 | 30.6 MHz | 40 nm | |
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| The IP is an UTMI+ Level 3 compatible USB2.0 OTG function transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel data for high speed and full speed. It is also support full speed and low speed serial mode. | 概述 | |||||
| WiFi Frequency Synthesizer IP In 2.4GHz Band | 100000 点 | 200.000 K μm^2 | 3.2 GHz | 55 nm | |
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| The frequency synthesizer uses a single 1.25V power supply. Good noise immunity allows this IP to be integrated in a noisy SOC environment. The synthesizer operates at 1.5X WiFi 2.4GHz band for wireless application. | 概述 | |||||
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