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| 14-Bit 3 MSPS ADC in GSMC110nm | 参考报价 | 322.000 K μm^2 | 3 MHz | 110 nm |  |
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| MCR_GS110_ADC14 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. | 概述 | |||||
| 14-Bit 1MSPS DAC in GSMC110nm | 参考报价 | 75.000 K μm^2 | 1 MHz | 110 nm | |
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| MIC_DAC14 is compact and low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from 1.7V to 5.6V. Its single-end output ranges from 0.1 to 0.9 of supply voltage. | 概述 | |||||
| 10-Bit 165 MSPS ADC in TSMC110nm | 参考报价 | 210.000 μm^2 | 165 MHz | 110 nm | |
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| MIC_ADC10 is compact and low power 10-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture and it is optimized for low power Figure 1. BLOCK DIAGRAM and small area. | 概述 | |||||
| 10-bit 300 MSPS Video DAC IP in 90 nm | 60000 点 | 76.000 K μm^2 | 300 MHz | 90 nm | |
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| The UIP_DAC10-300M_205370 is a 10-bit DAC designed in low power TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2V, in unsigned format. A 3.3V supply is used for the analog portion of the IP. This high performance DAC is designed for CVBS standard or RGB Video signal bandwidth. The IP consumes only 41 mA at 300 MSPS operation and utilizes a silicon area of only 0.076 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The DAC output current is 6-bit programmable. The IP architecture is robust and can be ported to other 90 nm processes. APPLICATIONS Composite Video (CVBS) HDTV RGB Video DAC Output Model | 概述 | |||||
| Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm | 参考报价 | 330.000 μm^2 | 330 MHz | 90 nm | |
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| is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. | 概述 | |||||
| Rapid IO PHY in 65nm | 参考报价 | 2.295 μm^2 | 25 Hz | 65 nm | |
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| The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). | 概述 | |||||
| Dual-Channel 12-bit 80 MSPS ADC IP in UMC 65 nm | 参考报价 | 450.000 μm^2 | 0.8 MHz | 65 nm | |
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| ADC X is an ultra-compact and very low power analog-to-digital converter (ADC) IP. The 12-bit 80 MSPS Dual ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. IP architecture is robust and can be ported to other 65 nm processes.The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. | 概述 | |||||
| WiFi Frequency Synthesizer IP In 2.4GHz Band | 100000 点 | 200.000 K μm^2 | 3.2 GHz | 55 nm | |
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| The frequency synthesizer uses a single 1.25V power supply. Good noise immunity allows this IP to be integrated in a noisy SOC environment. The synthesizer operates at 1.5X WiFi 2.4GHz band for wireless application. | 概述 | |||||
| Low power oscillator | 12000 点 | 100.100 μm^2 | 32 KHz | 40 nm | |
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| OSC32K is designed for 40nm advance process with 1.2v to 3.3v wide power(VDD) range. | 概述 | |||||
| USB2.0 OTG PHY in 40 nm | 80000 点 | 257.556 K μm^2 | 30.6 MHz | 40 nm | |
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| The IP is an UTMI+ Level 3 compatible USB2.0 OTG function transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel data for high speed and full speed. It is also support full speed and low speed serial mode. | 概述 | |||||
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