10-bit 300 MSPS Video DAC IP in 90 nm |
60000 点 |
76.000 K μm^2 |
300 MHz |
90 nm |
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The UIP_DAC10-300M_205370 is a 10-bit DAC designed in low power TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2V, in unsigned format.
A 3.3V supply is used for the analog portion of the IP. This high performance DAC is designed for CVBS standard or RGB Video signal bandwidth. The IP consumes only 41 mA at 300 MSPS operation and utilizes a silicon area of only 0.076 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems.
The DAC output current is 6-bit programmable. The IP architecture is robust and can be ported to other 90 nm processes.
APPLICATIONS
Composite Video (CVBS)
HDTV
RGB Video
DAC Output Model
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概述 |
10-bit 165 MSPS ADC IP in 28 nm |
80000 点 |
70.000 K μm^2 |
165 MHz |
28 nm |
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UIP_ADC10_165M_564144 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.
The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.
The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm^2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.
UIP_ADC10_165M_564144 can be used in the following applications:
‧Digital imaging
‧TV/Video
‧Wireless LAN
‧Rx communication channel
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概述 |
10-bit 165 MSPS ADC IP in 28 nm |
80000 点 |
70.000 K μm^2 |
165 MHz |
28 nm |
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UIP_ADC10_165M_809744 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.
The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.
The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.
UIP_ADC10_165M_809744 can be used in the following applications:
‧Digital imaging
‧TV/Video
‧Wireless LAN
‧Rx communication channel
‧IOT
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概述 |
10-bit 165 MSPS ADC IP in 130 nm |
70000 点 |
210.000 K μm^2 |
165 MHz |
130 nm |
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UIP_ADC10_165M_166413 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.
The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.
The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.
UIP_ADC10_165M_166413 can be used in the following applications:
‧Digital imaging
‧TV/Video
‧Wireless LAN
‧Rx communication channel
‧IOT
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概述 |
[110nm] 10-bit 165 MSPS ADC IP |
70000 点 |
210.000 K μm^2 |
165 MHz |
110 nm |
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UIP_ADC10_165M_213779 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.
The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.
The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.
UIP_ADC10_165M_213779 can be used in the following applications:
‧Digital imaging
‧TV/Video
‧Wireless LAN
‧Rx communication channel
‧IOT
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概述 |
10-Bit 165 MSPS ADC in TSMC110nm |
参考报价 |
210.000 μm^2 |
165 MHz |
110 nm |
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MIC_ADC10 is compact and low power 10-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture and it is optimized for low power Figure 1. BLOCK DIAGRAM and small area.
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概述 |
10-bit 80 MSPS ADC IP in 130 nm |
60000 点 |
210.000 K μm^2 |
80 MHz |
130 nm |
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UIP_ADC10_80M_156287 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.
The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.
The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.
UIP_ADC10_80M_156287 can be used in the following applications:
‧Digital imaging
‧TV/Video
‧Wireless LAN
‧Rx communication channel
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概述 |
[110nm]10-bit 80 MSPS ADC IP |
60000 点 |
210.000 K μm^2 |
80 MHz |
110 nm |
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UIP_ADC10_80M_183288 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.
The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.
The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.
UIP_ADC10_80M_183288 can be used in the following applications:
‧Digital imaging
‧TV/Video
‧Wireless LAN
‧Rx communication channel
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概述 |
12-Bit 50 MSPS ADC in IBM 180 SOI |
参考报价 |
280.000 μm^2 |
50 MHz |
180 nm |
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MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area.
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概述 |
PLL 1300M UMC 28 nm logic and Mixed-Mode HPC process |
参考报价 |
109.850 K μm^2 |
50 MHz |
28 nm |
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It is used to generate a stable, high-speed clock from an external slower clock signal. It integrates one Voltage-Controlled Oscillator (VCO), one Phase-Frequency Detector (PFD), one Low-Pass Filter (LPF), one 8-bit programmable divider, and other associated support circuitries. This PLL supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. This IP uses the input operating frequency of PFD ranging from 6 MHz to 25 MHz and generates the output frequency ranging from 25 MHz to 1300 MHz.
The jitter performance of a PLL is highly dependent on the floor plan of ASIC. Because PLL is a sensitive cell when integrated into an ASIC design, the best way to maximize its capacity is to keep PLL away from the noisy blocks in the core region, such as the memory block and the high-driving logic circuit, and the I/O region, such as the high-driving I/O. This PLL must be placed around the I/O area. Providing sufficient space between this PLL and the noisy blocks is a simple and effective approach to reduce the coupled substrate noise.
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概述 |