客服
中
心
| 10-bit 80 MSPS ADC IP in 130 nm | 60000 点 | 210.000 K μm^2 | 80 MHz | 130 nm |  |
|
| UIP_ADC10_80M_156287 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_80M_156287 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel | 概述 | |||||
| 4.2V-to-1.2V DC/DC Converter | 参考报价 | 40.000 K μm^2 | 1 MHz | 130 nm | |
|
| The DCDC12 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.05V to 1.3V.An external 10uH inductor is necessary. | 概述 | |||||
| 4.2V-to-1.8V DC/DC Converte | 参考报价 | 40.000 K μm^2 | 1 Hz | 130 nm | |
|
| The DCDC18 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.65V to 1.9V.An external 10uH inductor is necessary. | 概述 | |||||
| PLL with Multiple Output Frequency | 参考报价 | 40.000 K μm^2 | 12.156 MHz | 130 nm | |
|
| The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source. This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider. This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃. | 概述 | |||||
| Ultra-High Accuracy Bandgap Reference in 130 nm (VBRS1000NT130) | 参考报价 | 无资料 | 无资料 | 130 nm | |
|
| ACCUREF™ Bandgap Reference (Silicon-proven 40 nm, low-power, low-noise, ultra-precise single-digit mV accuracy, no external components required) ACCUREF™ Voltage and Current References: This series of low-power, low-noise IP cores generates a precise, adjustable reference voltage with single-digit millivolt (mV) accuracy over a wide temperature range without external components. With their unique design that improves upon current products by allowing the systems to operate with ultra-low levels of power consumption without sacrificing accuracy or noise performance, our family of ACCUREF™ voltage and current reference IP cores support a broad range of industry applications with improved efficiency and remarkable area savings overall. | 概述 | |||||
| 300 mA Capless LDO in 130 nm (VLDS0300LS130) | 参考报价 | 无资料 | 无资料 | 130 nm | |
|
| Power Quencher® Capless LDO (Silicon-proven 130 nm, 300 mA, excellent quiescent current and load transient regulation) The Power Quencher® series of fully-integrated low dropout (LDO) voltage regulators operates with ultra-low levels of power consumption without sacrificing other areas of performance. They achieve a low-noise output voltage and do not require the external output capacitor that is typically needed in an LDO for loop stability and noise reduction. This saves component count, board space and cost, and improves overall system reliability. The Power Quencher® LDO voltage regulator IP cores are optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and Internet of Things (IoT) applications. | 概述 | |||||
| 12-Bit 320MPS IQ DAC in TSMC40LP | 70000 点 | 250.000 K μm^2 | 320 MHz | 180 nm | |
|
| UIP_DAC12X2_320M_922687 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. This IQ DAC IP is optimized for low power and small area. At 320 MHz conversation rate, it only consumes 63mW and occupies silicon area of 0.25 mm2. APPLICATIONS WiFi / LTE / WiMax Wireless MIMO Digital Video Communication Transmit | 概述 | |||||
| 12-Bit 800KSPS Low Power SAR-ADC | 参考报价 | 无资料 | 25 MHz | 180 nm | |
|
| The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. | 概述 | |||||
| Oscillator - RC22MHz | 参考报价 | 无资料 | 22 MHz | 180 nm | |
|
| The RC_OSC22M is a low power consumption internal Resistor/Capacitor oscillator with trimming operating frequency. This OSC needs input Bandgap reference voltage to maintain stable operating frequency and decrease power supply effects. The RC-oscillator cell is useful for applications that require an oscillator that utilizes non-external components and has a relaxed frequency tolerance. An enable / disable mode is provided to disable the oscillator. When the oscillator is in the disable mode, the output (CLK22M) goes to a logic level low. It is processed using SMIC’s 0.35μm logic process with an operating supply voltage range of 2.0V ~ 5.5V and a junction temperature range of -40˚ ~ 125˚C. | 概述 | |||||
| 12-Bit 50 MSPS ADC in IBM 180 SOI | 参考报价 | 280.000 μm^2 | 50 MHz | 180 nm | |
|
| MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area. | 概述 | |||||
| 微IP | 价格 | 逻辑闸数 | 工作频率 | 工艺 | 评价 | |
|---|---|---|---|---|---|---|