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| MIPI M-PHY Gear 4 IP in TSMC 12nm FFC | 参考报价 | 无资料 | 11 GHz | 12 nm |  |
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| MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. | 概述 | |||||
| 8-Bit 7 GSPS SAR ADC | 参考报价 | 300.000 K μm^2 | 7 GHz | 16 nm | |
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| This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area. APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition | 概述 | |||||
| WiFi Frequency Synthesizer IP In 2.4GHz Band | 100000 点 | 200.000 K μm^2 | 3.2 GHz | 55 nm | |
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| The frequency synthesizer uses a single 1.25V power supply. Good noise immunity allows this IP to be integrated in a noisy SOC environment. The synthesizer operates at 1.5X WiFi 2.4GHz band for wireless application. | 概述 | |||||
| 2.4G PLL(UMC 28nm HPC) | 参考报价 | 24.000 K μm^2 | 2.4 GHz | 28 nm | |
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| Clock output 2.4GHz Input clock 10 ~ 50MHz Current consumption: < 4mA Supply: 1.8V / 0.9V UMC 28nm HPC | 概述 | |||||
| PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process | 参考报价 | 230.000 μm^2 | 2 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate an accurate clock. | 概述 | |||||
| PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process | 参考报价 | 270.000 μm^2 | 1.6 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz. This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate a high-speed clock. The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz. | 概述 | |||||
| PLL 800M UMC 28 nm logic and Mixed-Mode HPC process | 参考报价 | 230.000 μm^2 | 800 MHz | 28 nm | |
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| It is a 28-nm low-power spread spectrum clock generator that supports an operating frequency ranging from 400 MHz to 800 MHz and from 200 MHz to 400 MHz. This SSCG is programmable to perform the frequency synthesis and spread-spectrum function for the Electro Magnetic Interference (EMI) reduction in various ASIC designs. | 概述 | |||||
| Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm | 参考报价 | 330.000 μm^2 | 330 MHz | 90 nm | |
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| is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. | 概述 | |||||
| 12-Bit 320MPS IQ DAC in TSMC40LP | 70000 点 | 250.000 K μm^2 | 320 MHz | 180 nm | |
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| UIP_DAC12X2_320M_922687 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. This IQ DAC IP is optimized for low power and small area. At 320 MHz conversation rate, it only consumes 63mW and occupies silicon area of 0.25 mm2. APPLICATIONS WiFi / LTE / WiMax Wireless MIMO Digital Video Communication Transmit | 概述 | |||||
| 12-Bit 320MSPS IQ DAC in IBM SOI 180nm | 参考报价 | 254.000 K μm^2 | 320 MHz | 180 nm | |
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| MIC_DAC12X2 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. | 概述 | |||||
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