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| 4.2V-to-1.2V DC/DC Converter | 参考报价 | 40.000 K μm^2 | 1 MHz | 130 nm |  |
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| The DCDC12 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.05V to 1.3V.An external 10uH inductor is necessary. | 概述 | |||||
| 4.2V-to-1.8V DC/DC Converte | 参考报价 | 40.000 K μm^2 | 1 Hz | 130 nm | |
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| The DCDC18 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.65V to 1.9V.An external 10uH inductor is necessary. | 概述 | |||||
| PLL with Multiple Output Frequency | 参考报价 | 40.000 K μm^2 | 12.156 MHz | 130 nm | |
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| The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source. This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider. This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃. | 概述 | |||||
| 14-Bit 3 MSPS ADC in GSMC110nm | 60000 点 | 32.000 K μm^2 | 3 MHz | 110 nm | |
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| UIP_ADC14_3M_245303 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low power and small area. The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. This ADC consumes 150 uA at 3 MSPS operation and occupies silicon area of 0.32 mm2 . The ADC has high immunity to substrate noise and is ideal for SoC integration. APPLICATIONS General purpose data acquisition Battery monitory system Temperature monitory system | 概述 | |||||
| 2.4G PLL(UMC 28nm HPC) | 参考报价 | 24.000 K μm^2 | 2.4 GHz | 28 nm | |
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| Clock output 2.4GHz Input clock 10 ~ 50MHz Current consumption: < 4mA Supply: 1.8V / 0.9V UMC 28nm HPC | 概述 | |||||
| 12-Bit 800KSPS Low Power SAR-ADC | 参考报价 | 无资料 | 25 MHz | 180 nm | |
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| The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. | 概述 | |||||
| Dual-Channel 12-bit 80 MSPS ADC IP in UMC 65 nm | 参考报价 | 450.000 μm^2 | 0.8 MHz | 65 nm | |
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| ADC X is an ultra-compact and very low power analog-to-digital converter (ADC) IP. The 12-bit 80 MSPS Dual ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. IP architecture is robust and can be ported to other 65 nm processes.The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. | 概述 | |||||
| Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm | 参考报价 | 330.000 μm^2 | 330 MHz | 90 nm | |
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| is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. | 概述 | |||||
| 12-Bit 50 MSPS ADC in IBM 180 SOI | 参考报价 | 280.000 μm^2 | 50 MHz | 180 nm | |
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| MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area. | 概述 | |||||
| PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process | 参考报价 | 270.000 μm^2 | 1.6 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz. This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate a high-speed clock. The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz. | 概述 | |||||
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