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| DSP-BASED ETHERNET TRANSCEIVER in UMC 28nm HPC+ | 参考报价 | 无资料 | 25 MHz | 28 nm |  |
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| A 28nm DPS-based Gigabit Ethernet transceiver. Highly intergrated 1000BASE-T, 100BASE-TX, 100BASE-FX and 10BASE-Te. Fully compliant with 100BASE-FX IEEE 802.2u standard | 概述 | |||||
| PCI Express Gen4 PHY IP in 28nm HPC+ | 参考报价 | 无资料 | 25 MHz | 28 nm | |
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| The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. | 概述 | |||||
| PCI Express Gen4 PHY IP in TSMC 12nm FFC | 参考报价 | 无资料 | 25 MHz | 12 nm | |
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| The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. | 概述 | |||||
| 微IP | 价格 | 逻辑闸数 | 工作频率 | 工艺 | 评价 | |
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