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BRAINS 50000 点 5.250 K Gates 1.2 GHz 40 nm  
With improvement of technology node and IC design is geting more complex, the ratio of embedded memory in SoCs have been exceeding 50%. The fault types of memory are getting complex. The Memory BIST (Built-In Self-Test) is generated for efficient controlling IC cost. The traditional BIST method is inserted along with single memory. If there are many memories in SoCs, the area and testing time of SoCs are expanded a lot due to insertion of BIST. Therefore the SoCs' cost will increase rapidly because memory testing time is too long.  We devoted in developing SRAM testing solutions for a long time. BRAINS is based on memory testing patents to reduce testing time and increase yield rate. In addition, BRAINS has many unique features to increase SoCs' reliability and stability.   概述
USB2.0 OTG PHY in 40 nm 80000 点 257.556 K μm^2 30.6 MHz 40 nm  
The IP is an UTMI+ Level 3 compatible USB2.0 OTG function  transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis  comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel  data for high speed and full speed. It is also support full speed and low speed  serial mode. 概述
12-Bit 800KSPS Low Power SAR-ADC 参考报价 无资料 25 MHz 180 nm  
The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC   and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. 概述
Low power oscillator 12000 点 100.100 μm^2 32 KHz 40 nm  
OSC32K is designed for 40nm advance process with 1.2v to 3.3v wide power(VDD) range.    概述
12-Bit 320MPS IQ DAC in TSMC40LP 70000 点 250.000 K μm^2 320 MHz 180 nm  
UIP_DAC12X2_320M_922687  is  compact  and low  power  12-bit  digital-to-analog  converter silicon  IP  in  IBM  180nm  SOI  process.  It features two channel current steering DAC.  This  IQ  DAC  IP  is  optimized  for  low  power and  small  area.  At  320  MHz  conversation rate,  it  only  consumes  63mW  and  occupies silicon area of 0.25 mm2.   APPLICATIONS​ WiFi / LTE / WiMax​ Wireless MIMO Digital Video Communication Transmit   概述
14 Bit Rail to Rail DAC 60000 点 75.000 K μm^2 1 MHz 110 nm  
UIP_DAC14_1M_392231  is  compact  and  low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from  1.7V  to  5.6V.  Its  single-end  output ranges from 0.1 to 0.9 of supply voltage.     This DAC IP is self-biased and optimized for low  power  and  small  area.   At 1 MHz conversation rate, it only consumes 680uA to drive  15K/50pF  loading  and  occupies  silicon area of 0.075 mm2.   APPLICATIONS General purpose digital to analog converter Battery monitory system Housekeeping Auxiliary functionality 概述
14-Bit 3 MSPS ADC in GSMC110nm 60000 点 32.000 K μm^2 3 MHz 110 nm  
UIP_ADC14_3M_245303  is  compact  and  low power 14-bit analog-to-digital converter silicon IP.  It  has  20  single-end  input  channel selection  multiplexer  or  10  differential  input channels  selection.  This  ADC  uses  fully differential SAR architecture optimized for low power and small area. The ADC is designed for  high  dynamic  performance  for  input frequencies  up  to  Nyquist  rate.  This  ADC consumes  150  uA  at  3  MSPS  operation  and occupies  silicon  area  of  0.32 mm2 .  The  ADC has  high  immunity  to  substrate  noise  and  is ideal  for  SoC  integration.   APPLICATIONS  General purpose data acquisition Battery monitory system  Temperature monitory system 概述
AES Codec with 128-bit datapath 20000 点 22.000 K Gates 260 MHz 180 nm  
The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of  data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed for high throughput applications with optimal logic resources utilization. The encryptor core accepts a 128-bit plaintext input word, and generates a corresponding 128-bit ciphertext output word using a supplied 128, 192, or 256-bit AES key. The decryptor core provides the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The hardware roundkey expansion logic has been designed as a discrete building block. This allows either to build a complete stand-alone AES solution, or to save logic resources by leaving the key generation process to the user. Alternatively, the roundkey expansion logic can be shared between multiple encryption/decryption cores for optimal silicon area resources utilization. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications.  概述
AES Codec with 8-bit datapath 20000 点 1.300 K Gates 515 MHz 180 nm  
The IP core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. The IP has been carefully designed to require minimum logic resources rendering it an ideal solution for low power applications. This has been achieved by using an 8-bit data path size which means that 16 clock cycles are required to load/unload the 128-bit plaintext/ciphertext block. The encryptor receives the 128-bit plaintext block in 8-bit input symbols and generates the corresponding 128-bit ciphertext block in 8-bit output symbols using a supplied 128, 192, or 256-bit AES key. The pre-computed key values are read from an internal round key RAM. A key expander module is provided as an optional module to allow automatic generation and loading of the round key RAM. The decryptor implements the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications.  概述
Configurable Reed Solomon Encoder 30000 点 2.500 K Gates 250 MHz 180 nm  
Our IP core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It  also  supports  varying  on  the  fly   shortened  codes.  Therefore  any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst  decoding.  The  implementation  is  very  low  latency,  high  speed with a simple interface for easy integration in SoC applications. 概述
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