Contact Us   客

商城 > IP 商城

32 bits RISC Microcontroller 参考报价 33.000 K Gates 100 MHz 180 nm  
The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces. Applications Wearables IoT Motor Control Appliances Connectivity Smart home/building/enterprice/planet 概述
电流式感测器尿酸浓度检测 参考报价 无资料 无资料 无资料  
本电路为低功耗之电流输入电流输出,能感测的电流范围因输入端为低阻抗的关系,能量测的电流范围能从250pA~50uA。本电路共有48颗MOS,其中包含一个辅导放大器(OTA)、自体偏压放大器(OPA)与9颗低功率MOS,运用电流镜架构把输入电流复制到输出端,电路稳定度也不会随着溶液之等效阻抗而明显变动,使其能更稳定运作。利用电化学的安培法来量测葡萄糖氧化反应所产生的电流信号,输入电流式读出电路,做电流讯号处理,后端再以微控器处理电路输出讯号,并做数值的转换,转换成血糖值,最后显示在LCD上,完成一血糖机雏形。   应用领域: 血糖 尿酸 胆固醇 酒精浓度   专利取得 : 美国 中华民国     概述
8-Bit 7 GSPS SAR ADC 参考报价 300.000 K μm^2 7 GHz 16 nm  
This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area.     APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition 概述
USB2.0 UTMI Device PHY(non-oscillator) 100000 点 280.000 K μm^2 30.6 MHz 40 nm  
The USB PHY is an UTMI compatible USB2.0 device PHY IP which does not  require external oscillator reference. It is comprised of both USB1.1 and USB2.0  transceivers and it is also comprised of digital logic needed to convert USB serial  data to 8 or 16 bit parallel data. 概述
NVM test and repair 60000 点 5.250 K Gates 2.2 GHz 40 nm  
HEART (High Efficient Accumulative Repairing Technical) is a built-in self-repair (BISR) mechanism which uses to recover errors detected after memory testing and to improve yield rate. This mechanism is implemented with spare memories and a built-in redundancy analyze (BIRA) logics which is designed to allocate the redundancy. It needs a storable device (eFuse, OTP or registers) to store testing results after analysis. We provides an efficient accumulative repairing solution to combine advantages of soft BISR mechanism and hard BISR mechanism for improving yield rate. 概述
HEART(High Efficient Accumulative Repairing Technical) 50000 点 5.250 K Gates 2.2 GHz 40 nm  
HEART can efficient repair faulty SRAM after using BRAINS. SoCs can mantain correctness of functions and avoid fatal error of system reault in SRAM's defect through SRAM's repairing technical. HEART is SRAM accumulative repairing technical, and it combines advantages of Soft-repair and Hard-repair. HEART supports internal registers of SoCs and external storages of SoCs to record SRAM's faulty information. Once SoCs have new SRAM's defect after using them for a long time, users can repeated repair SRAM's defect through HEART. In addtion, HEART also support "On-Demad" testing and repairing requirement. It means that users can enable system registers of SoCs or signal of HEART to test and repair SRAM at one when SoCs have fatal error situations.   概述
BRAINS 50000 点 5.250 K Gates 1.2 GHz 40 nm  
With improvement of technology node and IC design is geting more complex, the ratio of embedded memory in SoCs have been exceeding 50%. The fault types of memory are getting complex. The Memory BIST (Built-In Self-Test) is generated for efficient controlling IC cost. The traditional BIST method is inserted along with single memory. If there are many memories in SoCs, the area and testing time of SoCs are expanded a lot due to insertion of BIST. Therefore the SoCs' cost will increase rapidly because memory testing time is too long.  We devoted in developing SRAM testing solutions for a long time. BRAINS is based on memory testing patents to reduce testing time and increase yield rate. In addition, BRAINS has many unique features to increase SoCs' reliability and stability.   概述
USB2.0 OTG PHY in 40 nm 80000 点 257.556 K μm^2 30.6 MHz 40 nm  
The IP is an UTMI+ Level 3 compatible USB2.0 OTG function  transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis  comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel  data for high speed and full speed. It is also support full speed and low speed  serial mode. 概述
12-Bit 800KSPS Low Power SAR-ADC 参考报价 无资料 25 MHz 180 nm  
The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC   and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. 概述
Low power oscillator 12000 点 100.100 μm^2 32 KHz 40 nm  
OSC32K is designed for 40nm advance process with 1.2v to 3.3v wide power(VDD) range.    概述
微IP 价格 逻辑闸数 工作频率 工艺   评价

 4  5  6  7  8  9  10  11  12  13