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I2C Slave Serial Interface Controller 参考报价 无资料 300 MHz 无资料  
Slave serial controller compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your ASIC device via a set of user-defined config and status registers. Supports standard (100 kbits/s), fast (400 kbits/s) and custom rates in excess of 4 Mbits/s.    Applications I2C slave communication via your ASIC Inter-chip board-level communications 概述
I2C Master Serial Interface Controller 参考报价 无资料 300 MHz 无资料  
Master serial controller compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from  ASIC device. Supports standard (100 kbits/s), fast (400 kbits/s) and custom data rates well above 4 Mbits/s. Setup and hold-times on the SDA pin are fully configurable.    Applications Inter-chip board-level communications Standard 2-wire comms between a wide range of peripherals, MCUs and COTs ICs   概述
UART Serial Interface Controller 参考报价 无资料 300 MHz 无资料  
UART compatible Serial Interface Controller with receive and transmit FIFOs and support for all standard bit rates from 9600 to 921600 baud.    Applications UART Communications RS232, RS422, RS485 etc. Micro-controller interfacing 概述
8051 Core 参考报价 无资料 无资料 无资料  
The 8051 has gained great popularity since its introduction and is estimated it is  used in a large percentage of all embedded system products.  The  basic  form  of  8051  core  includes  several  on-chip  peripherals,  like  timers  and  counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of  on-chip program memory. 概述
32 bits RISC Microcontroller 参考报价 33.000 K Gates 100 MHz 180 nm  
The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces. Applications Wearables IoT Motor Control Appliances Connectivity Smart home/building/enterprice/planet 概述
电流式感测器尿酸浓度检测 参考报价 无资料 无资料 无资料  
本电路为低功耗之电流输入电流输出,能感测的电流范围因输入端为低阻抗的关系,能量测的电流范围能从250pA~50uA。本电路共有48颗MOS,其中包含一个辅导放大器(OTA)、自体偏压放大器(OPA)与9颗低功率MOS,运用电流镜架构把输入电流复制到输出端,电路稳定度也不会随着溶液之等效阻抗而明显变动,使其能更稳定运作。利用电化学的安培法来量测葡萄糖氧化反应所产生的电流信号,输入电流式读出电路,做电流讯号处理,后端再以微控器处理电路输出讯号,并做数值的转换,转换成血糖值,最后显示在LCD上,完成一血糖机雏形。   应用领域: 血糖 尿酸 胆固醇 酒精浓度   专利取得 : 美国 中华民国     概述
8-Bit 7 GSPS SAR ADC 参考报价 300.000 K μm^2 7 GHz 16 nm  
This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area.     APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition 概述
USB2.0 UTMI Device PHY(non-oscillator) 100000 点 280.000 K μm^2 30.6 MHz 40 nm  
The USB PHY is an UTMI compatible USB2.0 device PHY IP which does not  require external oscillator reference. It is comprised of both USB1.1 and USB2.0  transceivers and it is also comprised of digital logic needed to convert USB serial  data to 8 or 16 bit parallel data. 概述
NVM test and repair 60000 点 5.250 K Gates 2.2 GHz 40 nm  
HEART (High Efficient Accumulative Repairing Technical) is a built-in self-repair (BISR) mechanism which uses to recover errors detected after memory testing and to improve yield rate. This mechanism is implemented with spare memories and a built-in redundancy analyze (BIRA) logics which is designed to allocate the redundancy. It needs a storable device (eFuse, OTP or registers) to store testing results after analysis. We provides an efficient accumulative repairing solution to combine advantages of soft BISR mechanism and hard BISR mechanism for improving yield rate. 概述
HEART(High Efficient Accumulative Repairing Technical) 50000 点 5.250 K Gates 2.2 GHz 40 nm  
HEART can efficient repair faulty SRAM after using BRAINS. SoCs can mantain correctness of functions and avoid fatal error of system reault in SRAM's defect through SRAM's repairing technical. HEART is SRAM accumulative repairing technical, and it combines advantages of Soft-repair and Hard-repair. HEART supports internal registers of SoCs and external storages of SoCs to record SRAM's faulty information. Once SoCs have new SRAM's defect after using them for a long time, users can repeated repair SRAM's defect through HEART. In addtion, HEART also support "On-Demad" testing and repairing requirement. It means that users can enable system registers of SoCs or signal of HEART to test and repair SRAM at one when SoCs have fatal error situations.   概述
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