IP 商城

Latest & Hot μIP :

商城 > IP 商城

Motion-adaptive Video Deinterlacer 参考报价 无资料 200 MHz 无资料  
The IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216  pixels. The design is fully programmable and supports any desired interlaced video format. The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document. The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely  generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3. Application Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips Studio-quality video de-interlacing 概述
Video Test Pattern Generator 参考报价 无资料 500 MHz 无资料  
The IP module  is a versatile test pattern generator capable of producing a range of test patterns in colour, greyscale and monochrome formats. The module is invaluable in the prototyping stages of digital video systems. In addition, the test pattern generator may be used to provide a blank background display. The video output resolution is controlled by the generic parameters "PPL" and "LPF".  The colour, type and dimensions of the test pattern are determined by the parameters  INTL,  MODE,  TYPE  and  LOG2W. Application Generation of a blank video background Simple screen savers Digital video testing and prototyping   概述
Video Timing Generator 参考报价 无资料 400 MHz 无资料  
The IP Core is a fully configurable video timing generator with the ability to support any video resolution up to 216  x 216 pixels in size. The module is compatible with a wide range of video DACs, CODECs and transceivers and provides a flexible solution for displaying digital or analogue video on an external TV, monitor or flat panel display.  The module is capable of clock speeds in excess of 400 MHz on some FPGA platforms, making it ideal for the latest generation HD and UHD video solutions. After resynchronizing the input pixels to the pixel-clock domain , the controller locks to the first frame (or field) of video. Once frame-lock is achieved, pixels are supplied on demand to the video timing control unit. This module generates the correct RGB video, sync and blanking information depending on the chosen timing parameters. Application Legacy (SD) and analogue video applications Digital TV and multimedia solutions HD, UHD and SUHD next generation digital video   概述
RF Power Amplifier Precorrection 参考报价 无资料 150 MHz 无资料  
The IP is a complete Digital Precorrection(Predistortion) system designed to compensate for the non-linear characteristic of a high-power RF Amplifier. The system is capable of adjusting both the gain and phase of a complex input signal.   This is achieved by means of a complex multiplication of the input with a complex polynomial function stored in the LT. The LT contains the inverse PA characteristic and is applied before the amplification stages (either at baseband or IF frequencies). By programming the LT with the inverse gain/phase PA  response,   the resultant PA response is linearized. After linearization, the output signal is much cleaner with reduced intermodulation distortion.  The system may be used in open-loop or closed-loop configuration. For open loop operation, the LUT coefficients are static and programmed during initial setup of the PA precorrection system. For   closed-loop operation, an external circuit may compare the baseband inputs and PA outputs and adjust the LUT coefficients dynamically in order to automate the linearization process. Application Precorrection of wide bandwidth signals such as UMTS, WCDMA and OFDM Power amplifier linearization for mobile Base-stations, Broadcasting etc. Precorrection of any type of digitally modulated signal where the signal envelope varies and therefore the instantaneous input power. 概述
Periodic waveform generator 参考报价 无资料 200 MHz 无资料  
The IP Core is a high-precision Direct Digital Synthesizer 2 used for the generation of periodic waveforms. On each rising-edge of the sample clock, the phase in the phase accumulator is incremented by the value phase_inc.  This phase is quantized to 16-bits and passed as an address to a look-up table which converts the phase into a waveform. In addition to the quadrature outputs sin_out and cos_out, the IP also provides square wave and sawtooth outputs: squ_out and  saw_out.  All output values are 16-bit signed numbers.  Appliaction Digital up/down converters and mixers Versatile waveform generation Digital oscillators Digital modulation 概述
Precision Tone Decoder 参考报价 无资料 200 MHz 无资料  
The IP is a precision tone decoder with the capacity to support either real or complex data samples. Samples are first mixed-down to baseband before subsequent filtering and tone detection. The centre frequency of the tone is fully programmable and is generated by a local oscillator (DDS).  The DDS has an SFDR of better than 80 dBs (with phase dithering) and a theoretical SNR of approximately 100 dBs. After down-conversion, 2 paths are filtered to remove components above the tone of interest.  The characteristics of these filters may be changed depending on the desired detection bandwidth and response time. Finally, a power function is used to compute the relative magnitude of the signal after filtering. Application Precision frequency monitoring and control FSK / OOK / ASK demodulation Touch tone decoding (e.g. DTMF tones) Complex digital down conversion   概述
USB 3.0 PHY in 110nm 参考报价 1.000 M μm^2 25 Hz 110 nm  
    The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification.  This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The  IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. 概述
Digital Video overlay module 参考报价 无资料 250 MHz 无资料  
This IP is a highly versatile video multiplexer that allows one video stream to be inserted over another.  By cascading a series of video overlay modules together, any number of video sources may be multiplexed together. The module supports input video streams of any resolution or aspect ratio up to 216   x 216  pixels in size. Video overlay parameters may be changed on a frame-by-frame basis to dynamically change the size and position of the video overlay. Pixels and syncs flow in and out of the video overlay module in accordance with the valid-ready pipeline protocol. The pipeline protocol allows both input and output interfaces to be stalled independently. In addition, the overlay module supports a number of blending operations including an 8-bit alpha channel and bitwise AND, OR and XOR functions. Application Network and Tactical operations centres Digital-video special effects Broadcast TV and film production CCTV and security camera systems 概述
2D Graphics Overlay 参考报价 无资料 200 MHz 无资料  
This is a highly versatile on-screen display that allows high-quality anti-aliased bitmap graphics to be inserted over RGB video. The module supports a wide range of graphics effects and the programming interface is very simple to use. The bitmap overlay is partitioned into an array of tiles which are addressed by means of an 8-bit value stored in a 64x64 tile buffer. There are four tile sizes available - either 8x8, 16x16, 32x32 or 64x64. The tiles in the buffer are displayed in a graphics window which may be positioned anywhere within the display area. Bitmaps for each tile are stored in a user-defined ROM which can contain up to  256  different bitmaps stored over three bit-planes. Depending on the chosen graphics mode, the 3-bits per pixel may be used to select one colour from a palette of eight, eight levels of alpha transparency or seven colours on a transparent background. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol. Application Animated 2D graphics including hardware sprites, mouse pointers, cursors , parallax scrolling, moving banners etc. Interactive guides, menus, tables, lists etc. Digital TV and home-media solutions Professional and functional 2D graphic displays and video overlays   概述
Text Overlay Module 参考报价 无资料 200 MHz 无资料  
The IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video.   The module supports a wide range of text effects and the programming interface is very simple.  Text is written to a 64x32 character buffer which is mapped (via a bitmap ROM) directly to the display. The characters in the buffer are displayed in a 'TEXT BOX' which may be positioned anywhere in the video display area. Bitmaps for each character are stored in a ROM which may be modified to support different font styles or bitmap graphics. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol.  Application Window movement in the same manner as a 2D 'BitBlt' Terminal and Console windows Low cost text and graphics applications Digital TV and home-media solutions 概述
微IP 价格 逻辑闸数 工作频率 工艺   评价

 1  2  3  4  5  6  7  8  9  10